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db cool ? remote thermal monitor and fan controller adt7467 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features controls and monitors up to 4 fans high and low frequency fan drive signal 1 on-chip and 2 remote temperature sensors series resistance cancellation on the remote channel extended temperature measurement range, up to 191c dynamic t min control mode optimizes system acoustics intelligently automatic fan speed control mo de controls system cooling based on measured temperature enhanced acoustic mode dramatically reduces user perception of changing fan speeds thermal protection feature via therm output monitors performance impact of intel? pentium? 4 processor thermal control circuit via therm input 2-wire, 3-wire, and 4-wire fan speed measurement limit comparison of all monitored values meets smbus 2.0 electrical specifications (fully smbus 1.1 compliant) general description the adt7467 db cool tm controller is a thermal monitor and multiple pwm fan controller for noise-sensitive or power- sensitive applications requiring active system cooling. the adt7467 can drive a fan using either a low or high frequency drive signal, monitor the temperature of up to two remote sensor diodes plus its own internal temperature, and measure and control the speed of up to four fans, so that they operate at the lowest possible speed for minimum acoustic noise. the automatic fan speed control loop optimizes fan speed for a given temperature. a unique dynamic t min control mode enables the system thermals/acoustics to be intelligently managed. the effectiveness of the system's thermal solution can be monitored using the therm input. the adt7467 also provides critical thermal protection to the system using the bidirectional therm pin as an output to prevent system or component overheating. functional block diagram 04498-0-001 input signal conditioning and analog multiplexer gnd serial bus interface scl sda value and limit registers limit comparators interrupt status registers band gap temp sensor v cc to adt7467 address pointer register pwm configuration registers interrupt masking v cc d1+ d1? d2+ d2? v ccp thermal protection performance monitoring pwm registers and controllers hf & lf pwm1 pwm2 pwm3 acoustic enhancement control band gap reference 10-bit adc adt7467 automatic fan speed control dynamic t min control fan speed counter tach1 tach2 tach3 tach4 src therm smbalert figure 1.
adt7467 rev. 0 | page 2 of 80 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 thermal characteristics .............................................................. 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 product description......................................................................... 9 comparison between adt7460 and adt7467 ....................... 9 recommended implementation............................................... 10 serial bus interface..................................................................... 11 write operations ........................................................................ 12 read operations ......................................................................... 13 smbus timeout .......................................................................... 13 voltage measurement input...................................................... 13 analog-to-digital converter .................................................... 13 input circuitry............................................................................ 14 voltage measurement registers................................................ 14 v ccp limit registers ................................................................... 14 additional adc functions for voltage measurements ........ 14 temperature measurement method ........................................ 15 series resistance cancellation.................................................. 17 factors affecting diode accuracy ........................................... 17 additional adc functions for temperature measurement. 19 limits, status registers, and interrupts ....................................... 20 limit values................................................................................. 20 status registers ........................................................................... 21 therm timer............................................................................ 23 laying out 2-wire and 3-wire fans ....................................... 28 operating from 3.3 v standby.................................................. 32 xnor tree test mode .............................................................. 33 power-on default ...................................................................... 33 programming the automatic fan speed control loop ............ 34 automatic fan control overview............................................ 34 step 1: hardware configuration.............................................. 35 recommended implementation 1 ........................................... 36 recommended implementation 2 ........................................... 37 step 2: configuring the mux................................................... 38 step 3: t min settings for thermal calibration channels....... 40 step 4: pwm min for each pwm (fan) output....................... 41 step 5: pwm max for pwm (fan) outputs.............................. 41 step 6: t range for temperature channels................................ 42 step 7: t therm for temperature channels ............................... 45 step 8: t hyst for temperature channels .................................. 46 dynamic t min control mode ................................................... 48 step 9: operating points for temperature channels ............. 50 step 10: high and low limits for temperature channels ... 51 step 11: monitoring therm ................................................... 53 enhancing system acoustics .................................................... 54 step 12: ramp rate for acoustic enhancement..................... 56 register tables ................................................................................ 59 adt7467 programming block diagram .................................... 77 outline dimensions ....................................................................... 78 ordering guide .......................................................................... 78 revision history revision 0: initial version
adt7467 rev. 0| page 3 of 80 specifications t a = t min to t max , v cc = v min to v max , unless otherwise noted. all voltages are measured with respect to gnd, unless otherwise specified. typicals are at t a = 25c and represent most likely parametric norm. logic inputs accept input high voltages up to v max even when device is operating down to v min . timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.0 v for a rising edge. smbus timing specifications are guaranteed by design and are not production tested. table 1. parameter min typ max unit test conditions/comments power supply supply voltage 3.0 3.3 5.5 v supply current, i cc 3 ma interface inactive, adc active 20 a standby mode temp-to-digital converter local sensor accuracy 1.5 c 0c t a 70c ?3.5 +2 c ?40c t a +100c ?4 +2 c ?40c t a +120c resolution 0.25 c remote diode sensor accuracy 0.5 1.5 c 0c t a 70c; 0c t d 120c ?3.5 +2 c 0c t a 105c; 0c t d 120c ?4.5 +2 c ?40c t a +120c; 0c t d +120c resolution 0.25 c remote sensor source current 6 a first current 36 ? second current 96 ? third current analog-to-digital converter (inclu ding mux and attenuators) total unadjusted error (tue) 1.5 % differential nonlinearity (dnl) 1 lsb 8 bits power supply sensitivity 0.1 %/v conversion time (voltage input) 11 ms averaging enabled conversion time (local temperature) 12 ms averaging enabled conversion time (remote temperature) 38 ms averaging enabled total monitoring cycle time 145 ms averaging enabled total monitoring cycle time 19 ms averaging disabled input resistance 40 80 100 k? for v cc channel 80 140 200 k? for all other channels fan rpm-to-digital converter accuracy 5 % 0c t a 70c, 3.3 v 7 % ?40c t a +120c, 3.3 v 10 % ?40c t a +120c, 5.5 v full-scale count 65,535 nominal input rpm 109 rpm fan count = 0xbfff 329 rpm fan count = 0x3fff 5000 rpm fan count = 0x0438 10000 rpm fan count = 0x021c internal clock frequency 85.5 90 94.5 khz 0c t a 70c, v cc = 3.3v 83.7 90 96.3 khz ?40c t a +120c, v cc = 3.3 v 81 90 99 khz ?40c t a +120c, v cc = 5.5 v
adt7467 rev. 0 | page 4 of 80 parameter min typ max unit test conditions/comments open-drain digital outputs, pwm1 to pwm3, xto current sink, i ol 8.0 ma output low voltage, v ol 0.4 v i out = ?8.0 ma, v cc = +3.3 v high level output current, i oh 0.1 1.0 a v out = v cc open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = ?4.0 ma, v cc = +3.3 v high level output current, i oh 0.1 1.0 a v out = v cc smbus digital inputs (scl, sda) input high voltage, v ih 2.0 v input low voltage, v il 0.4 v hysteresis 500 mv digital input logic levels (tach inputs) input high voltage, v ih 2.0 v 5.5 v maximum input voltage input low voltage, v il 0.8 v ?0.3 v minimum input voltage hysteresis 0.5 v p-p digital input logic levels (therm ) adtl+ input high voltage, v ih 0.75 v ccp v input low voltage, v il 0.4 v digital input current input high current, i ih ?1 a v in = v cc input low current, i il 1 a v in = 0 input capacitance, c in 5 pf serial bus timing 5 see figure 2 clock frequency, f sclk 10 400 khz glitch immunity, t sw 50 ns bus free time, t buf 4.7 s start setup time, t su;sta 4.7 s start hold time, t hd;sta 4.0 s scl low time, t low 4.7 s scl high time, t high 4.0 50 s scl, sda rise time, t r 1000 ns scl, sda fall time, t f 300 s data setup time, t su;dat 250 ns data hold time, t hd;dat 300 ns detect clock low timeout, t timeout 15 35 ms can be optionally disabled scl sd a ps sp t buf t hd; sta t hd; dat t su; dat t f t r t low t su; sta t high t hd; sta t su; sto 04498-0-002 figure 2. serial bus timing diagram
adt7467 rev. 0| page 5 of 80 absolute maximum ratings table 2. parameter rating positive supply voltage (v cc ) 5.5 v voltage on any input or output pin ?0.3 v to +6.5 v input current at any pin 5 ma package input current 20 ma maximum junction temperature (t jmax ) 150c storage temperature range ?65c to +150c lead temperature, soldering ir reflow peak temperature 220c lead temperature (soldering 10 s) 300c esd rating 1000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 16-lead qsop package: ja = 150c/w jc = 39c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adt7467 rev. 0 | page 6 of 80 pin configuration and fu nction descriptions 04498-0-003 adt7467 top view (not to scale) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 scl gnd v cc tach3 pwm2/smbalert tach1 tach2 pwm3 sda pwm1/xto v ccp d1+ d1? d2+ tach4/gpio/therm/smbalert d2? figure 3. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 scl digital input (open drain). smbus seri al clock input. requires smbus pull-up. 2 gnd ground pin for the adt7467. 3 v cc power supply. can be powered by 3.3 v standby, if monitoring in low power states is required. v cc is also monitored through this pin. the adt7467 can also be powered from a 5 v supply. setting bi t 7 of configuration register 1 (reg. 0x40) rescales the v cc input attenuators to correctly measure a 5 v supply. 4 tach3 digital input (open drain). fan tachometer input to measure speed of fan 3. can be reconfigured as an analog input (ain3) to measure the speed of 2-wire fans (low frequency mode only). 5 pwm2 digital output (open drain). requires 10 k? typical pull-up. pulse width modu lated output to control fan 2 speed. can be configured as a high or low frequency drive. smbalert digital output (open drain). this pin can be reconfigured as an smbalert interrupt output to signal out-of-limit conditions. 6 tach1 digital input (open drain). fan tachometer input to measure speed of fan 1. can be reconfigured as an analog input (ain1) to measure the speed of 2-wire fans (low frequency mode only). 7 tach2 digital input (open drain). fan tachometer input to measure speed of fan 2. can be reconfigured as an analog input (ain2) to measure the speed of 2-wire fans (low frequency mode only). 8 pwm3 digital i/o (open drain). pulse width modulated output to control the speed of fan 3 and fan 4. requires 10 k? typical pull-up. can be configured as a high or low frequency drive. 9 tach4 digital input (open drain). fan tachometer input to measure speed of fan 4. can be reconfigured as an analog input (ain4) to measure the speed of 2-wire fans (low frequency mode only). gpio general purpose open drain digital i/o. therm alternatively, the pin can be reco nfigured as a bidirectional therm pin, which can be used to time and monitor assertions on the therm input. for example, the pin ca n be connected to the prochot output of an intel pentium 4 processor or to the output of a trip point temperature sensor. this pin can be used as an output to signal overtemperature conditions. smbalert digital output (open drain). this pin can be reconfigured as an smbalert interrupt output to signal out-of-limit conditions. 10 d2? cathode connection to second thermal diode. 11 d2+ anode connection to second thermal diode. 12 d1? cathode connection to first thermal diode. 13 d1+ anode connection to first thermal diode. 14 v ccp analog input. monitors proce ssor core voltage (0 v ? 3 v). 15 pwm1 digital output (open drain). pulse- width modulated output to co ntrol fan 1 speed. requires 10 k? typical pull-up. xto also functions as the output from the xnor tree in xnor test mode. 16 sda digital i/o (open drain). smbus bidirectional serial data. requires 10 k? typical pull-up.
adt7467 rev. 0| page 7 of 80 typical performance characteristics 04498-0-045 capacitance (nf) 1 4.7 3.3 10 0 2.2 temperature error (c) ?60 0 ?20 ?50 ?30 ?10 ?40 figure 4. temperature error vs. capacitance between d+ and d? 04498-0-046 capacitance (nf) 25 01020 515 temperature error (c) ?100 0 ?20 ?50 ?30 ?60 ?70 ?80 ?90 ?10 ?40 figure 5. external temperature error vs. d+/d? capacitance 04498-0-047 resistance (m ? ) 100 0 3.3 20 110 temperature error (c) ?80 60 20 ?40 0 ?60 40 ?20 d+ to gnd d+ to v cc figure 6. temperature error vs. pcb resistance 04498-0-048 frequency (khz) 1g 10 100 1m 10m 100m temperature error (c) ?10 20 15 0 10 ?5 5 100mv 40mv 60mv figure 7. remote temperature error vs. common mode noise frequency 04498-0-049 frequency (khz) 1g 10 100 1m 10m 100m temperature error (c) ?4 6 4 ?2 2 ?3 0 5 ?1 3 1 10mv 20mv figure 8. remote temperature error vs. differential mode noise frequency 04498-0-050 power supply voltage (v) 3.0 3.8 5.2 3.4 4.4 3.6 4.8 3.2 4.0 5.4 4.6 5.0 4.2 i dd (ma) 1.05 1.40 1.30 1.20 1.15 1.10 1.35 1.25 figure 9. normal i dd vs. power supply
adt7467 rev. 0 | page 8 of 80 04498-0-051 power supply voltage (v) 3.0 3.8 5.2 3.4 4.4 3.6 4.8 3.2 4.0 5.4 4.6 5.0 4.2 i dd ( a) 0 7 5 3 2 1 6 4 figure 10. shutdown i dd vs. power supply 04498-0-052 power supply noise frequency (khz) 1g 10 100 1m 10m 100m temperature error (c) ?20 20 10 ?5 5 ?10 ?15 15 0 int error, 100mv int error, 250mv figure 11. internal temperature error vs. power supply 04498-0-053 power supply noise frequency (khz) 1g 10 100 1m 10m 100m temperature error (c) ?20 20 10 ?5 5 ?10 ?15 15 0 ext error, 100mv ext error, 250mv figure 12. remote temperature error vs. power supply noise frequency 04498-0-091 temperature (c) 120 ?40 ?20 0 20 40 60 80 100 temperature error (c) 1.0 0 0.5 ?1.0 ?0.5 ?2.0 ?1.5 ?2.5 ?3.5 ?3.0 ?4.0 figure 13. internal temperature error vs. adt7467 temperature 04498-0-092 temperature (c) 120 ?40 ?20 0 20 40 60 80 100 temperature error (c) 1.0 0 0.5 ?1.0 ?0.5 ?2.0 ?1.5 ?2.5 ?3.5 ?3.0 ?4.0 figure 14. remote temperature error vs. adt7467 temperature
adt7467 rev. 0| page 9 of 80 product description the adt7467 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. the device communicates with the system via a serial system management bus. the serial bus controller has a serial data line for reading and writing addresses and data (pin 16), and an input line for the serial clock (pin 1). all control and programming functions for the adt7467 are performed over the serial bus. in addition, a pin can be reconfigured as an smbalert output to signal out-of-limit conditions. comparison between ad t7460 and adt7467 the adt7467 is an upgrade to the adt7460. the adt7467 and adt7460 are almost pin and register map compatible. the adt7467 and adt7460 have the following differences: 1. on the adt7467, the pwm drive signals can be config- ured as either high frequency or low frequency drives. the low frequency option is programmable between 10 hz and 100 hz. the high frequency option is 22.5 khz. on the adt7460, only the low frequency option is available. 2. once v cc is powered up, monitoring of temperature and fan speeds is enabled on the adt7467 when v ccp is powered up, or if v ccp is never powered up, when the first smbus transaction with the adt7467 is completed. on the adt7460, the strt bit in configuration register 1 must be set to enable monitoring. 3. the fans are switched off by default on power-up on the adt7467. on the adt7460, the fans run at full speed on power-up. fail-safe cooling is provided on the adt7467 in that, if the measured temperature exceeds the therm limit (100c), the fans run at full speed. fail-safe cooling is also provided 4.6 s after v ccp is powered up. the fans go to full speed, if the adt7467 has not been addressed via the smbus within 4.6 s of when the v ccp is powered up. this protects the system in the event that the smbus fails. the adt7467 can be programmed at any time, either before or after the 4.6 s has elapsed, and it behaves as programmed. if v ccp is never powered up, fail- safe cooling is effectively disabled. if v ccp is disabled, writing to the adt7467 at any time causes the adt7467 to operate normally. 4. series resistance cancellation (src) is provided on the remote temperature channels on the adt7467, but not on the adt7460. src automatically cancels linear offset introduced by a series resistance between the thermal diode and the sensor. 5. the adt7467 has an extended temperature measurement range. the measurement range goes fromC64c to +191c. on the adt7460, the measurement range is from ?127c to +127c. this means that the adt7467 can measure higher temperatures. the adt7467 also includes the adt7460 temperature range; the temperature measure- ment range can be switched by setting bit 0 of configuration register 5. 6. the adt7467 maximum fan speed (% duty cycle) in the automatic fan speed control loop can be programmed. the maximum fan speed is 100% duty cycle on the adt7460 and is not programmable. 7. the offset register in the adt7467 is programmable up to 64c with 0.50c resolution. the offset register of the adt7460 is programmable up to 32c with 0.25c resolution. 8. v ccp is monitored on pin 14 of the adt7467 and can be used to set the threshold for therm ( prochot ) (2/3 of v ccp ). 2.5 v is monitored on pin 14 of the adt7460. the threshold for therm ( prochot ) is set at v ih = 1.7 v and v il = 0.8 v on the adt7460. 9. on the adt7460, pin 14 could be reconfigured as smbus alert. this is not available on the adt7467. smbus alert can be enabled instead on pin 9. 10. a gpio can also be made available on pin 9 on the adt7467. this is not available on the adt7460. set the gpio polarity and direction in configuration register 5. the gpio status bit is bit 5 of status register 2 (shared with tach4 and therm , because only one can be enabled at a time). 11. the adt7460 has three possible smbus addresses, which are selectable using the address select and address enable pins. the adt7467 has one smbus address available at address 0x2e. due to the inclusion of extra functionality, the register map has changed, including an additional configuration register: configuration register 5 at address 0x7c.
adt7467 rev. 0 | page 10 of 80 configuration register 5 bit 0: if bit 0 is set to 1, the adt7467 is backward compatible temperature-wise with the adt7460. measurements, t min calibration circuit, fan control, etc., work in the range ?127c to +127c. also, care should be taken in reprogramming the temperature limits (t min , operating point, therm limits) to their desired twos complement value, because the power-on default for them is at offset 64. the extended temperature range is ?64c to 191c. the default is 1, which is in the ?64c to +191c temperature range. bit 1 = 0 is the high frequency (22.5 khz) fan drive signal. bit 1 = 1 switches the fan drive to low frequency pwm, programmable between 10 hz and 100 hz, the same as the adt7460. the default = 0 = hf pwm. bit 2 sets the direction for the gpio: 0 = input, 1 = output. bit 3 sets the gpio polarity: 0 = active low, 1 = active high. how to set the functionality of pin 9 pin 9 on the adt7467 has four possible functions: smbalert , therm , gpio, and tach4. the user chooses the required functionality by setting bit 0 and bit 1 of configuration register 4 at address 0x7d. table 4. pin 9 settings bit 0 bit 1 function 00 tach4 01 therm 10 smbalert 11 gpio recommended implementation configuring the adt7467 as in figure 15 allows the system designer to use the following features: ? two pwm outputs for fan control of up to three fans (the front and rear chassis fans are connected in parallel). ? three tach fan speed measurement inputs. ? v cc measured internally through pin 3. ? cpu temperature measured using remote 1 temperature channel. ? ambient temperature measured through remote 2 temperature channel. ? bidirectional therm pin. this feature allows intel pentium 4 prochot monitoring and can function as an overtemperature therm output. it can alternatively be programmed as an smbalert system interrupt output. cpu fan cpu ich tach2 pwm3 tach3 d1+ d1? gnd adt7467 scl sda d2+ d2? tach1 pwm1 ambient temperature smbalert therm 04498-0-004 prochot front chassis fan rear chassis fan figure 15. adt7467 configuration
adt7467 rev. 0| page 11 of 80 serial bus interface on pcs and servers, control of the adt7467 is carried out using the serial system management bus (smbus). the adt7467 is connected to this bus as a slave device, under the control of a master controller, which is usually (but not necessarily) the ich. the adt7467 has a fixed 7-bit serial bus address of 0101110 or 0x2e. the read/write bit must be added to get the 8-bit address (01011100 or 0x5c). data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master then takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the adt7467, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, then data can be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the address pointer register. this write operation is illustrated in figure 16. the device address is sent over the bus, and then r/ w is set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. when reading data from a register, there are two possibilities: ? if the adt7467s address pointer register value is unknown or not the desired value, it must first be set to the correct value before data can be read from the desired data register. this is done by performing a write to the adt7467 as before, but only the data byte containing the register address is sent, because no data is written to the register. this is shown in figure 17. a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte read from the data register. this is shown in figure 18. ? if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in figure 18. r/w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7467 start by master 19 1 ack. by adt7467 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7467 stop by master 1 9 scl (continued) sda (continued) frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte 04498-0-005 figure 16. writing a register address to the address pointe r register, then writing data to the selected register
adt7467 rev. 0 | page 12 of 80 r/w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7467 stop by master start by master frame 1 serial bus address byte frame 2 address pointer register byte 1 1 9 ack. by adt7467 9 04498-0-006 figure 17. writing to the address pointer register only r/w 0 scl s d a 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. by master stop by master start by master frame 1 serial bus address byte frame 2 data byte from adt7467 1 1 9 ack. by adt7467 9 04498-0-007 figure 18. reading data from a previously selected register it is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. however, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. in addition to supporting the send byte and receive byte protocols, the adt7467 also supports the read byte protocol. (see system management bus specifications rev. 2 for more information. this document is available from intel.) if several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. write operations the smbus specification defines several protocols for different types of read and write operations. the ones used in the adt7467 are discussed below. the following abbreviations are used in the diagrams: s C start p C stop r C read w C write a C acknowledge a C no acknowledge the adt7467 uses the following smbus write protocols. send byte in this operation, the master device sends a single command byte to a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. for the adt7467, the send byte protocol is used to write a register address to ram for a subsequent single byte read from the same address. this operation is illustrated in figure 19. slave address wa sap register address 23 156 4 04498-0-008 figure 19. setting a register address for subsequent read if the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ack and carry out a single byte read without asserting an intermediate stop condition. write byte in this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code.
adt7467 rev. 0| page 13 of 80 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction. this operation is illustrated in figure 20. slave address slave address data a a w sap 246 5 3 178 04498-0-009 figure 20. single byte write to a register read operations the adt7467 uses the following smbus read protocols. receive byte this operation is useful when repeatedly reading a single register. the register address must have been set up previously. in this operation, the master device receives a single byte from a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts no ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. in the adt7467, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. this operation is illustrated in figure 21. slave address sraap data 2 1356 4 04498-0-010 figure 21. single byte read from a register alert response address alert response address (ara) is a feature of smbus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. the smbalert output can be used as either an interrupt output or an smbalert . one or more outputs can be connected to a common smbalert line connected to the master. if a devices smbalert line goes low, the following procedure occurs: 1. smbalert is pulled low. 2. the master initiates a read operation and sends the alert response address (ara = 0001 100). this is a general call address that must not be used as a specific device address. 3. the device whose smbalert output is low responds to the alert response address, and the master reads its device address. the address of the device is now known and can be interrogated in the usual way. 4. if more than one devices smbalert output is low, the one with the lowest device address has priority in accor- dance with normal smbus arbitration. 5. once the adt7467 has responded to the alert response address, the master must read the status registers and the smbalert is cleared only if the error condition has gone away. smbus timeout the adt7467 includes an smbus timeout feature. if there is no smbus activity for 35 ms, the adt7467 assumes that the bus is locked and releases the bus. this prevents the device from locking or holding the smbus expecting data. some smbus controllers cannot handle the smbus timeout feature, so it can be disabled. configuration register 1(reg. 0x40) <6> todis = 0, smbus timeout enabled (default). <6> todis = 1, smbus timeout disabled. voltage measurement input the adt7467 has one external voltage measurement channel. it can also measure its own supply voltage, v cc . pin 14 can meas- ure v ccp . the v cc supply voltage measurement is carried out through the v cc pin (pin 3). setting bit 7 of configuration register 1 (reg. 0x40) allows a 5 v supply to power the adt7467 and be measured without overranging the v cc measurement channel. the v ccp input can be used to monitor a chipset supply voltage in computer systems. analog-to-digital converter all analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. this has a resolu- tion of 10 bits. the basic input range is 0 v to 2.25 v, but the input has built-in attenuators to allow measurement of v ccp without any external components. to allow for the tolerance of the supply voltage, the adc produces an output of 3/4 full scale (decimal 768 or 300 hex) for the nominal input voltage and so has adequate headroom to deal with overvoltages.
adt7467 rev. 0 | page 14 of 80 input circuitry the internal structure for the v ccp analog input is shown in figure 22. the input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order low- pass filter that gives the input immunity to high frequency noise. v ccp 17.5k ? 52.5k ? 35pf 04498-0-011 figure 22. structure of analog inputs voltage measurement registers reg. 0x21 v ccp reading = 0x00 default reg. 0x22 v cc reading = 0x00 default v ccp limit registers associated with the v ccp and v cc measurement channels is a high and low limit register. exceeding the programmed high or low limit causes the appropriate status bit to be set. exceeding either limit can also generate smbalert interrupts. reg. 0x46 v ccp low limit = 0x00 default reg. 0x47 v ccp high limit = 0xff default reg. 0x48 v cc low limit = 0x00 default reg. 0x49 v cc high limit = 0xff default table 5 shows the input ranges of the analog inputs and output codes of the 10-bit adc. when the adc is running, it samples and converts a voltage input in 0.7 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11 ms. additional adc functions for voltage measurements a number of other functions are available on the adt7467 to offer the system designer increased flexibility. turn-off averaging for each voltage measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. for instances where faster conversions are needed, setting bit 4 of configuration register 2 (reg. 0x73) turns averaging off. this effectively gives a reading 16 times faster (0.7 ms), but the reading may be noisier. bypass voltage input attenuator setting bit 5 of configuration register 2 (reg. 0x73) removes the attenuation circuitry from the v ccp input. this allows the user to directly connect external sensors or to rescale the analog voltage measurement inputs for other applications. the input range of the adc without the attenuators is 0 v to 2.25 v. single-channel adc conversion setting bit 6 of configuration register 2 (reg. 0x73) places the adt7467 into single-channel ad c conversion mode. in this mode, the adt7467 can be made to read a single voltage channel only. if the internal adt7467 clock is used, the selected input is read every 0.7 ms. the appropriate adc channel is selected by writing to bits <7:5> of the tach1 minimum high byte register (0x55). bits <7:5> reg. 0x55 channel selected 001 v ccp 010 v cc 101 remote 1 temperature 110 local temperature 111 remote 2 temperature configuration register 2 (reg. 0x73) <4> = 1, averaging off. <5> = 1, bypass input attenuators. <6> = 1, single-channel convert mode. tach1 minimum high byte (reg. 0x55) <7:5> selects adc channel for single-channel convert mode.
adt7467 rev. 0| page 15 of 80 table 5. 10-bit a/d output code vs. v in input voltage a/d output v cc (+5 v in ) v cc (3.3 v in ) v ccp decimal binary (10 bits) <0.0065 <0.0042 <0.00293 0 00000000 00 0.0065C0.0130 0.0042C0.0085 0.0293C0.0058 1 00000000 01 0.0130C0.0195 0.0085C0.0128 0.0058C0.0087 2 00000000 10 0.0195C0.0260 0.0128C0.0171 0.0087C0.0117 3 00000000 11 0.0260C0.0325 0.0171C0.0214 0.0117C0.0146 4 00000001 00 0.0325C0.0390 0.0214C0.0257 0.0146C0.0175 5 00000001 01 0.0390C0.0455 0.0257C0.0300 0.0175C0.0205 6 00000001 10 0.0455C0.0521 0.0300C0.0343 0.0205C0.0234 7 00000001 11 0.0521C0.0586 0.0343C0.0386 0.0234C0.0263 8 00000010 00 ? ? ? 1.6675C1.6740 1.100C1.1042 0.7500C0.7529 256 (1/4-scale) 01000000 00 ? ? ? 3.330C3.3415 2.200C2.2042 1.5000C1.5029 512 (1/2-scale) 10000000 00 ? ? ? 5.0025C5.0090 3.300C3.3042 2.2500C2.2529 768 (3/4 scale) 11000000 00 ? ? ? 6.5983C6.6048 4.3527C4.3570 2.9677C2.9707 1013 11111101 01 6.6048C6.6113 4.3570C4.3613 2.9707C2.9736 1014 11111101 10 6.6113C6.6178 4.3613C4.3656 2.9736C2.9765 1015 11111101 11 6.6178C6.6244 4.3656C4.3699 2.9765C2.9794 1016 11111110 00 6.6244C6.6309 4.3699C4.3742 2.9794C2.9824 1017 11111110 01 6.6309C6.6374 4.3742C4.3785 2.9824C2.9853 1018 11111110 10 6.6374C6.4390 4.3785C4.3828 2.9853C2.9882 1019 11111110 11 6.6439C6.6504 4.3828C4.3871 2.9882C2.9912 1020 11111111 00 6.6504C6.6569 4.3871C4.3914 2.9912C2.9941 1021 11111111 01 6.6569C6.6634 4.3914C4.3957 2.9941C2.9970 1022 11111111 10 >6.6634 >4.3957 >2.9970 1023 11111111 11 temperature measurement method a simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the base- emitter voltage (v be ) of a transistor, operated at constant current. unfortunately, this technique requires calibration to null out the effect of the absolute value of v be , which varies from device to device. the technique used in the adt7467 is to measure the change in v be when the device is operated at three different currents. previous devices have used only two operating currents, but the use of a third current allows automatic cancellation of resistances in series with the external temperature sensor. figure 24 shows the input signal conditioning used to measure the output of an external temperature sensor. this figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor. if a discrete transistor is used, the collector is not grounded and should be linked to the base. to prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the d? input. c1 can optionally be added as a noise filter (recommended maximum value 1000 pf). however, a better option in noisy environments is to add a filter, as described in the noise filtering section.
adt7467 rev. 0 | page 16 of 80 local temperature measurement the adt7467 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit adc. the 8-bit msb temperature data is stored in the local tempera- ture register (address 26h). because both positive and negative temperatures can be measured, the temperature data is stored in offset 64 format or twos complement format, as shown in table 6 and table 7. theoretically, the temperature sensor and adc can measure temperatures from ?128c to +127c (or ?61c to +191c in the extended temperature range) with a resolution of 0.25c. however, this exceeds the operating temperature range of the device, so local temperature measurements outside the adt7467 operating temperature range are not possible. remote temperature measurement the adt7467 can measure the temperature of two remote diode sensors or diode-connected transistors connected to pins 10 and 11, or 12 and 13. the forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about C2 mv/c. unfortunately, the absolute value of v be varies from device to device and individual calibration is required to null this out, so the technique is unsuitable for mass production. the technique used in the adt7467 is to measure the change in v be when the device is operated at three different currents. this is given by () n n q kt v be 1 / = ? where: k is boltzmanns constant. q is the charge on the carrier. t is the absolute temperature in kelvin. n is the ratio of the two currents. figure 23 shows the input signal conditioning used to measure the output of a remote temperature sensor. this figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. it could also be a discrete transistor such as a 2n3904/2n3906. n2 i in1 ii bias d+ d? lpf v dd v out+ v out? f c = 65khz to adc 04498-0-012 remote sensing transistor figure 23. signal conditioning for remote diode temperature sensors if a discrete transistor is used, the collector is not grounded and should be linked to the base. if a pnp transistor is used, the base is connected to the dC input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the dC input and the base to the d+ input. figure 25 and figure 26 show how to connect the adt7467 to an npn or pnp transistor for temperature measurement. to prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the dC input. to me a su re ? v be , the operating current through the sensor is switched among three related currents. shown in figure 23, n1 i and n2 i are different multiples of the current i. the currents through the temperature diode are switched between i and n1 i, giving ? v be1 , and then between i and n2 i, giving ? v be2 . the temperature can then be calculated using the two ? v be measurements. this method can also cancel the effect of any series resistance on the temperature measurement. the resulting ?v be waveforms are passed through a 65 khz low-pass filter to remove noise and then to a chopper-stabilized amplifier. this amplifies and rectifies the waveform to produce a dc voltage proportional to ?v be . the adc digitizes this voltage, and a temperature measurement is produced. to reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. the results of remote temperature measurements are stored in 10-bit, twos complement format, as listed in table 6. the extra resolution for the temperature measurements is held in the extended resolution register 2 (reg. 0x77). this gives temperature readings with a resolution of 0.25c. noise filtering for temperature sensors operating in noisy environments, previous practice was to place a capacitor across the d+ and d? pins to help combat the effects of noise. however, large capaci- tances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pf. this capacitor reduces the noise, but does not eliminate it, making use of the sensor difficult in a very noisy environment.
adt7467 rev. 0| page 17 of 80 the adt7467 has a major advantage over other devices for eliminating the effects of noise on the external sensor. using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the part. the effect of any filter resistance seen in series with the remote sensor is automatically canceled from the temperature result. the construction of a filter allows the adt7467 and the remote temperature sensor to operate in noisy environments. figure 24 shows a low-pass r-c-r filter, with the following values: r = 100 ?, c = 1 nf this filtering reduces both common-mode noise and differential noise. 04498-0-093 d+ 1nf 100 ? remote t emperature sensor d? 100 ? figure 24. filter between remote sensor and adt7467 series resistance cancellation parasitic resistance to the adt7467 d+ and d? inputs (seen in series with the remote diode) is caused by a variety of factors including pcb track resistance and track length. this series resistance appears as a temperature offset in the remote sensors temperature measurement. this error typically causes a 0.5c offset per 1 ? of parasitic resistance in series with the remote diode. the adt7467 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result without the need for user characterization of this resistance. the adt7467 is designed to automatically cancel, typically, up to 3 k? of resistance. by using an advanced temperature measurement method, this is transparent to the user. this feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. see the noise filtering section for details. factors affecting diode accuracy remote sensing diode the adt7467 is designed to work with either substrate transistors built into processors or discrete transistors. substrate transistors are generally pnp types with the collector connected to the substrate. discrete types can be either pnp or npn transistors connected as a diode (base-shorted to the collector). if an npn transistor is used, the collector and base are connected to d+ and the emitter is connected to d?. if a pnp transistor is used, the collector and base are connected to d? and the emitter is connected to d+. to reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: ? the ideality factor, n f , of the transistor is a measure of the deviation of the thermal diode from ideal behavior. the adt7467 is trimmed for an n f value of 1.008. use the following equation to calculate the error introduced at a temperature t (c), when using a transistor whose n f does not equal 1.008. see the processor data sheet for the n f values. ? t = ( n f ? 1.008)/1.008 (273.15 k + t ) to factor this in, the user can write the ? t value to the offset register. the adt7467 then automatically adds it to or subtracts it from the temperature measurement. ? some cpu manufacturers specify the high and low current levels of the substrate transistors. the high current level of the adt7467, i high , is 96 a and the low level current, i low , is 6 a. if the adt7467 current levels do not match the current levels specified by the cpu manufacturer, it might be necessary to remove an offset. the cpus data sheet advises whether this offset needs to be removed and how to calculate it. this offset can be programmed to the offset register. it is important to note that, if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register. if a discrete transistor is used with the adt7467, the best accuracy is obtained by choosing devices according to the following criteria: ? base-emitter voltage greater than 0.25 v at 6 a, at the highest operating temperature. ? base-emitter voltage less than 0.95 v at 100 a, at the lowest operating temperature. ? base resistance less than 100 ?. ? small variation in h fe (say 50 to 150) that indicates tight control of v be characteristics. transistors, such as 2n3904, 2n3906, or equivalents in sot-23 packages, are suitable devices to use.
adt7467 rev. 0 | page 18 of 80 table 6. temperature data format temperature digital output (10-bit) 1 C128c 1000 0000 00 C125c 1000 0011 00 C100c 1001 1100 00 C75c 1011 0101 00 C50c 1100 1110 00 C25c 1110 0111 00 C10c 1111 0110 00 0c 0000 0000 00 10.25c 0000 1010 01 25.5c 0001 1001 10 50.75c 0011 0010 11 75c 0100 1011 00 100c 0110 0100 00 125c 0111 1101 00 127c 0111 1111 00 1 bold numbers denote 2 lsb of measurement in extended resolution register 2 (reg. 0x77) with 0.25c resolution. table 7. extended range, temperature data format temperature digital output (10-bit) 1 C64c 0000 0000 00 C1c 0011 1111 00 0c 0100 0000 00 1c 0100 0001 00 10c 0100 1010 00 25c 0101 1001 00 50c 0111 0010 00 75c 1000 1001 00 100c 1010 0100 00 125c 1011 1101 00 191c 1111 1111 00 1 bold numbers denote 2 lsb of measurement in extended resolution register 2 (reg. 0x77) with 0.25c resolution. 2n3904 npn adt7467 d+ d? 04498-0-013 figure 25. measuring temperature using an npn transistor 2n3906 pnp adt7467 d+ d? 04498-0-014 figure 26. measuring temperature using a pnp transistor nulling out temperature errors as cpus run faster, it is getting more difficult to avoid high frequency clocks when routing the d+/dC traces around a system board. even when recommended layout guidelines are followed, some temperature errors may still be attributable to noise coupled onto the d+/dC lines. constant high frequency noise usually attenuates or increases temperature measurements by a linear, constant value. the adt7467 has temperature offset registers at addresses 0x70, 0x72 for the remote 1 and remote 2 temperature channels. by doing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. the offset registers auto- matically add an offset 64/twos complement 8-bit reading to every temperature measurement. the lsbs add 0.5c offset to the temperature reading so the 8-bit register effectively allows temperature offsets of up to 64c with a resolution of 0.5c. this ensures that the readings in the temperature measurement registers are as accurate as possible. temperature offset registers reg. 0x70 remote 1 temperature offset = 0x00 (0c default) reg. 0x71 local temperature offset = 0x00 (0c default) reg. 0x72 remote 2 temperature offset = 0x00 (0c default) adt7460/adt7467 backward s compatible mode by setting bit 1 of configuration register 5 (0x7c), all tempera- ture measurements are stored in the zone temp value registers (0x25, 0x26, and 0x27) in twos complement in the range ?64c to +127c. (the adt7468 still makes calculations based on the offset64 extended range and clamps the results, if necessary.) the temperature limits must be reprogrammed in twos comple- ment. if a twos complement temperature below ?63c is entered, the temperature is clamped to ?63c. in this mode, the diode fault condition remains ?128c = 1000 0000, while in the extended temperature range (?64c to +191c), the fault condition is represented by ?64c = 0000 0000. temperature measurement registers reg. 0x25 remote 1 temperature reg. 0x26 local temperature reg. 0x27 remote 2 temperature reg. 0x77 extended resolution 2 = 0x00 default <7:6> tdm2 , remote 2 temperature lsbs. <5:4> ltmp , local temperature lsbs. <3:2> tdm1 , remote 1 temperature lsbs.
adt7467 rev. 0| page 19 of 80 temperature measurement limit registers associated with each temperature measurement channel are high and low limit registers. exceeding the programmed high or low limit causes the appropriate status bit to be set. exceeding either limit can also generate smbalert interrupts. reg. 0x4e remote 1 temperature low limit = 0x01 default reg. 0x4f remote 1 temperature high limit = 0x7f default reg. 0x50 local temperature low limit = 0x01 default reg. 0x51 local temperature high limit = 0x7f default reg. 0x52 remote 2 temperature low limit = 0x01 default reg. 0x53 remote 2 temperature high limit = 0x7f default reading temperature from the adt7467 it is important to note that temperature can be read from the adt7467 as an 8-bit value (with 1c resolution) or as a 10-bit value (with 0.25c resolution). if only 1c resolution is required, the temperature readings can be read back at any time and in no particular order. if the 10-bit measurement is required, this involves a 2-register read for each measurement. the extended resolution register (reg. 0x77) should be read first. this causes all temperature reading registers to be frozen until all temperature reading registers have been read from. this prevents an msb reading from being updated while its two lsbs are being read and vice versa. additional adc functions for temperature measurement a number of other functions are available on the adt7467 to offer the system designer increased flexibility. turn-off averaging for each temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. sometimes it is necessary to take a very fast measurement. setting bit 4 of configuration register 2 (reg. 0x73) turns averaging off. table 8. conversion time with averaging disabled channel measurement time voltage channel 0.7 ms remote temperature 1 7 ms remote temperature 2 7 ms local temperature 1.3 ms table 9. conversion time with averaging enabled channel measurement time voltage channels 11 ms remote temperature 39 ms local temperature 12 ms single-channel adc conversions setting bit 6 of configuration register 2 (reg. 0x73) places the adt7467 into single-channel ad c conversion mode. in this mode, the adt7467 can be made to read a single temperature channel only. the appropriate adc channel is selected by writing to bits <7:5> of the tach1 minimum high byte register (0x55). table 10. channel selection bits <7:5> reg. 0x55 channel selected 101 remote 1 temperature 110 local temperature 111 remote 2 temperature configuration register 2 (reg. 0x73) <4> = 1, averaging off. <6> = 1, single-channel convert mode, tach1 minimum high byte (reg. 0x55) <7:5> selects adc channel for single-channel convert mode. overtemperature events overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. reg. 0x6a to reg. 0x6c are the therm temperature limits. when a temperature exceeds its therm temperature limit, all pwm outputs run at the maximum pwm duty cycle (reg. 0x38, reg. 0x39, reg. 0x3a). this effectively runs the fans at the fastest allowed speed. the fans stay running at this speed until the temperature drops below therm minus hysteresis. (this can be disabled by setting the boost bit in configuration register 3, bit 2, reg. 0x78.) the hysteresis value for that therm temperature limit is the value programmed into reg. 0x6d and reg. 0x6e (hysteresis registers). the default hysteresis value is 4c. fans temperature 100% hysteresis (c) therm limit 04498-0-015 figure 27. therm temperature limit operation
adt7467 rev. 0 | page 20 of 80 limits, status registers, and interrupts limit values associated with each measurement channel on the adt7467 are high and low limits. these can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and detected by polling the device. alternatively, smbalert interrupts can be generated to flag a processor or microcontroller of out-of-limit conditions. 8-bit limits the following is a list of 8-bit limits on the adt7467. voltage l imit re g isters reg. 0x46 v ccp low limit = 0x00 default reg. 0x47 v ccp high limi t = 0xff default reg. 0x48 v cc low limit = 0x00 default reg. 0x49 v cc high limit = 0xff default temperature limit registers reg. 0x4e remote 1 temperature low limit = 0x01 default reg. 0x4f remote 1 temperature high limit = 0x7f default reg. 0x6a remote 1 therm limit = 0x64 default reg. 0x50 local temperature low limit = 0x01 default reg. 0x51 local temperature high limit = 0x7f default reg. 0x6b local therm limit = 0x64 default reg. 0x52 remote 2 temperature low limit = 0x01 default reg. 0x53 remote 2 temperature high limit = 0x7f default reg. 0x6c remote 2 therm limit = 0x64 default therm limit register reg. 0x7a therm limit = 0x00 default 16-bit limits the fan tach measurements are 16-bit results. the fan tach limits are also 16 bits, consisting of a high byte and low byte. because fans running under speed or stalled are normally the only conditions of interest, only high limits exist for fan tachs. because the fan tach period is actually being measured, exceeding the limit indicates a slow or stalled fan. fan limit registers reg. 0x54 tach1 minimum l ow byte = 0x00 default reg. 0x55 tach1 minimum high byte = 0x00 default reg. 0x56 tach2 minimum l ow byte = 0x00 default reg. 0x57 tach2 minimum high byte = 0x00 default reg. 0x58 tach3 minimum l ow byte = 0x00 default reg. 0x59 tach3 minimum high byte = 0x00 default reg. 0x5a tach4 minimum l ow byte = 0x00 default reg. 0x5b tach4 minimum high byte = 0x00 default out-of-limit comparisons once all limits have been programmed, the adt7467 can be enabled for monitoring. the adt7467 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit for out-of-limit conditions. tach measurements are not part of this round-robin cycle. compari- sons are done differently depending on whether the measured value is being compared to a high or low limit. high limit: > comparison performed low limit: comparison performed voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. fan speed measurements use only a low limit. this fan limit is needed only in manual fan control mode. analog monitoring cycle time the analog monitoring cycle begins when a 1 is written to the start bit (bit 0) of configuration register 1 (reg. 0x40). by default, the adt7463 powers up with this bit set. the adc measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropriate value register. this round-robin monitoring cycle continues unless disabled by writing a 0 to bit 0 of configuration register 1. as the adc is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can be read out at any time. for applications where the monitoring cycle time is important, it can easily be calculated. the total number of channels measured is ? one dedicated supply voltage input (v ccp ) ? supply voltage (v cc pin) ? local temperature ? two remote temperatures
adt7467 rev. 0| page 21 of 80 as mentioned previously, the adc performs round-robin conversions . the total monitoring cycle time for averaged voltage and temperature monitoring is 145 ms. the total monitoring cycle time for voltage and temperature monitoring with averaging disabled is 19 ms. the adt7467 is a derivative of the adt7468. as a result, the total conversion time in the adt7467 is the same as the total conversion time of the adt7468, even though the adt7467 has less monitored channels. fan tach measurements are made in parallel and are not synchronized with the analog measurements in any way. status registers the results of limit comparisons are stored in status registers 1 and 2. the status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. if a measurement is within limits, the corresponding status register bit is cleared to 0. if the measurement is out-of-limits, the corresponding status register bit is set to 1. the state of the various measurement channels can be polled by reading the status registers over the serial bus. in bit 7 (ool) of status register 1 (reg. 0x41), 1 means that an out-of-limit event has been flagged in status register 2. this means that the user also needs to read status register 2. alternatively, pin 5 or pin 9 can be configured as an smbalert output. this hardware interrupt automatically notifies the system supervisor of an out- of-limit condition. reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. status register bits are sticky. whenever a status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). the only way to clear the status bit is to read the status register after the event has gone away. interrupt status mask registers (reg. 0x74, 0x75) allow individual interrupt sources to be masked from causing an smbalert . however, if one of these masked interrupt sources goes out-of- limit, its associated status bit is set in the interrupt status registers. status register 1 (reg. 0x41) bit 7 (ool) = 1 , denotes a bit in status register 2 is set and status register 2 should be read. bit 6 (r2t) = 1 , remote 2 temperature high or low limit has been exceeded. bit 5 (lt) = 1 , local temperature high or low limit has been exceeded. bit 4 (r1t) = 1 , remote 1 temperature high or low limit has been exceeded. bit 2 (v cc ) = 1, v cc high or low limit has been exceeded. bit 1 (v ccp ) = 1 , v ccp high or low limit has been exceeded. status register 2 (reg. 0x42) bit 7 (d2) = 1 , indicates an open or short on d2+/d2C inputs. bit 6 (d1) = 1 , indicates an open or short on d1+/d1C inputs. bit 5 (f4p) = 1 , indicates fan 4 has dropped below minimum speed. alternatively, indicates that the therm limit has been exceeded, if the therm function is used. bit 4 (fan3) = 1 , indicates fan 3 has dropped below minimum speed. bit 3 (fan2) = 1 , indicates fan 2 has dropped below minimum speed. bit 2 (fan1) = 1 , indicates fan 1 has dropped below minimum speed. bit 1 (ovt) = 1 , indicates a therm overtemperature limit has been exceeded. smbalert interrupt behavior the adt7467 can be polled for status, or an smbalert interrupt can be generated for out-of-limit conditions. it is important to note how the smbalert output and status bits behave when writing interrupt handler software. ?sticky? status bi t high limit temperature cleared on read (temp below limit) temp back in limit (status bit stays set) smbalert 04498-0-022 figure 28. smbalert and status bit behavior figure 28 shows how the smbalert output and sticky status bits behave. once a limit is exceeded, the corresponding status bit is set to 1. the status bit remains set until the error condition subsides and the status register is read. the status bits are referred to as sticky, because they remain set until read by software. this ensures that an out-of-limit event cannot be missed, if software is polling the device periodically. note that the smbalert output remains low for the entire duration that a reading is out-of-limit and until the status register has been read. this has implications on how software handles the interrupt.
adt7467 rev. 0 | page 22 of 80 handling smbalert interrupts to prevent the system from being tied up servicing interrupts, it is recommend to handle the smbalert interrupt as follows: 1. detect the smbalert assertion. 2. enter the interrupt handler. 3. read the status registers to identify the interrupt source. 4. mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (reg. 0x74, reg. 0x75). 5. take the appropriate action for a given interrupt source. 6. exit the interrupt handler. 7. periodically poll the status registers. if the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. this causes the smbalert output and status bits to behave as shown in figure 29. ?sticky? status bit high limit temperature cleared on read (temp below limit) temp back in limit (status bit stays set) interrupt mask bit set smbalert 04498-0-023 interrupt mask bit cleared (smbalert rearmed) figure 29. how masking the interrupt source affects smbalert output masking interrupt sources interrupt mask registers 1 and 2 are located at addresses 0x74 and 0x75. these allow individual interrupt sources to be masked out to prevent smbalert interrupts. note that masking an interrupt source prevents only the smbalert output from being asserted; the appropriate status bit is set normally. interrupt mask register 1 (reg. 0x74) bit 7 (ool) = 1 , masks smbalert for any alert condition flagged in status register 2. bit 6 (r2t) = 1 , masks smbalert for remote 2 temperature. bit 5 (lt) = 1 , masks smbalert for local temperature. bit 4 (r1t) = 1 , masks smbalert for remote 1 temperature. bit 2 (v cc ) = 1 , masks smbalert for v cc channel. bit 0 (v ccp ) = 1 , masks smbalert for v ccp channel. interrupt mask register 2 (reg. 0x75) bit 7 (d2) = 1 , masks smbalert for diode 2 errors. bit 6 (d1) = 1 , masks smbalert for diode 1 errors. bit 5 (fan4) = 1 , masks smbalert for fan 4 failure. if the tach4 pin is being used as the therm input, this bit masks smbalert for a therm event. bit 4 (fan3) = 1 , masks smbalert for fan 3. bit 3 (fan2) = 1 , masks smbalert for fan 2. bit 2 (fan1) = 1 , masks smbalert for fan 1. bit 1 (ovt) = 1 , masks smbalert for overtemperature (exceeding therm temperature limits). enabling the smbalert interrupt output the smbalert interrupt function is disabled by default. pin 5 or pin 9 can be reconfigured as an smbalert output to signal out-of-limit conditions. table 11. configuring pin 5 as smbalert output register bit setting configuration register 3 (reg. 0x78) <0> alert = 1 assigning therm functionality to a pin pin 9 on the adt7467 has four possible functions: smbus alert, therm , gpio, and tach4. the user chooses the required functionality by setting bit 0 and bit 1 of configura- tion register 4 at address 0x7d. table 12. configuring pin 9 bit 0 bit 1 function 00 tach4 01 therm 10 smbus alert 11 gpio once pin 9 is configured as therm , it must be enabled (bit 1, configuration register 3 at address 0x78). therm as an input when therm is configured as an input, the user can time assertions on the therm pin. this can be useful for connect- ing to the prochot output of a cpu to gauge system performance.
adt7467 rev. 0| page 23 of 80 the user can also set up th e adt7467 so that, when the therm pin is driven low externally, the fans run at 100%. the fans run at 100% for the duration of the time that the therm pin is pulled low. this is done by setting the boost bit (bit 2) in configuration register 3 (address = 0x78) to 1. this works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above t min . if the temperature is below t min or if the duty cycle in manual mode is set to 0x00, then pulling the therm low externally has no effect. see figure 30 for more information. therm t min therm asserted to low as an input: fans do not go to 100%, because temperature is below t min therm asserted to low as an input: fans do not go to 100%, because temperature is above t min and fans are already running 04498-0-024 figure 30. asserting therm low as an input in automatic fan speed control mode therm timer the adt7467 has an internal timer to measure therm assertion time. for example, the therm input can be connected to the prochot output of a pentium 4 cpu to measure system performance. the therm input can also be connected to the output of a trip point temperature sensor. the timer is started on the assertion of the adt7467s therm input and stopped when therm is unasserted. the timer counts therm times cumulatively, that is, the timer resumes counting on the next therm assertion. the therm timer continues to accumulate therm assertion times until the timer is read (it is cleared on read) or until it reaches full scale. if the counter reaches full scale, it stops at that reading until cleared. the 8-bit therm timer register (reg. 0x79) is designed such that bit 0 is set to 1 on the first therm assertion. once the cumulative therm assertion time has exceeded 45.52 ms, bit 1 of the therm timer is set and bit 0 now becomes the lsb of the timer with a resolution of 22.76 ms (see figure 31). when using the therm timer, be aware of the following. after a therm timer read (reg. 0x79): 1. the contents of the timer are cleared on read. 2. the f4p bit (bit 5) of status register 2 needs to be cleared (assuming that the therm timer limit has been exceeded). if the therm timer is read during a therm assertion, then the following happens: 1. the contents of the timer are cleared. 2. bit 0 of the therm timer is set to 1 (because a therm assertion is occurring). 3. the therm timer increments from zero. 4. if the therm timer limit (reg. 0x7a) = 0x00, then the f4p bit is set. therm therm timer (reg. 0x79) therm asserted 22.76ms 765 3210 4 000 0001 0 therm timer (reg. 0x79) therm asserted 45.52ms 765 3210 4 000 0010 0 therm timer (reg. 0x79) therm asserted 113.8ms (91.04ms + 22.76ms) 765 3210 4 000 0101 0 therm accumulate therm low assertion times therm accumulate therm low assertion times 04498-0-025 figure 31.understanding the therm timer
adt7467 rev. 0 | page 24 of 80 generating smbalert interrupts from therm timer events the adt7467 can generate smbalert s when a programma- ble therm timer limit has been exceeded. this allows the system designer to ignore brief, infrequent therm assertions, while capturing longer therm timer events. register 0x7a is the therm timer limit register. this 8-bit register allows a limit from 0 s (first therm assertion) to 5.825 s to be set before an smbalert is generated. the therm timer value is compared with the contents of the therm timer limit register. if the therm timer value exceeds the therm timer limit value, then the f4p bit (bit 5) of status register 2 is set, and an smbalert is generated. note that the f4p bit (bit 5) of mask register 2 (reg. 0x75) masks out smbalert s, if this bit is set to 1; although the f4p bit of interrupt status register 2 still is set, if the therm timer limit is exceeded. figure 32 is a functional block diagram of the therm timer, limit, and associated circuitry. writing a value of 0x00 to the therm timer limit register (reg. 0x7a) causes smbalert to be generated on the first therm assertion. a therm timer limit value of 0x01 generates an smbalert , once cumulative therm assertions exceed 45.52 ms. 22.76ms 45.52ms 91.04ms 182.08ms 364.16ms 728.32ms 1.457s 2.914s in out reset latch cleared on read f4p bit (bit 5) mask register 2 (reg. 0x75) 1 = mask f4p bit (bit 5) status register 2 comparator 22.76ms 45.52ms 91.04ms 182.08ms 364.16ms 728.32ms 1.457s 2.914s 7 6 5 4 3 2 1 0 7 6 543 2 10 therm timer limit (reg. 0x7a) therm timer (reg. 0x79) therm timer cleared on read smbalert therm 04498-0-026 figure 32. functional block diagram of adt7467s therm monitoring circuitry
adt7467 rev. 0| page 25 of 80 configuring the therm behavior 1. configure the relevant pin as the therm timer input. setting bit 1 ( therm timer enable) of configuration register 3 (reg. 0x78) enables the therm timer monitoring functionality. this is disabled on pin 9 by default. setting bits 0 and 1 (pin9func) of configuration register 4 (reg. 0x7d) enables therm timer/output functionality on pin 9 (bit 1 of configuration register 3, therm , must also be set). pin 9 can also be used as tach4. 2. select the desired fan behavior for therm timer events. assuming that the fans are running, setting bit 2 (boost bit) of configuration register 3 (reg. 0x78) causes all fans to run at 100% duty cycle whenever therm gets asserted. this allows fail-safe system cooling. if this bit is 0, the fans run at their current settings and are not affected by therm events. if the fans are not already running when therm is asserted, the fans do not run to full speed. 3. select whether therm timer events should generate smbalert interrupts. bit 5 (f4p) of mask register 2 (reg. 0x75), when set, masks out smbalert s when the therm timer limit value gets exceeded. this bit should be cleared if smbalert s based on therm events are required. 4. select a suitable therm limit value. this value determines whether an smbalert is generated on the first therm assertion, or only if a cumulative therm assertion time limit is exceeded. a value of 0x00 causes an smbalert to be generated on the first therm assertion. 5. select a therm monitoring time. this value specifies how often os or bios level software checks the therm timer. for example, bios could read the therm timer once an hour to determine the cumulative therm assertion time. if, for example, the total therm assertion time is <22.76 ms in hour 1, >182.08 ms in hour 2, and >5.825 s in hour 3, this can indicate that system performance is degrading significantly because therm is asserting more frequently on an hourly basis. alternatively, os or bios level software can timestamp when the system is powered on. if an smbalert is generated due to the therm timer limit being exceeded, another timestamp can be taken. the difference in time can be calculated for a fixed therm timer limit time. for example, if it takes one week for a therm timer limit of 2.914 s to be exceeded and the next time it takes only 1 hour, then this is an indication of a serious degradation in system performance. configuring the therm pin as an output in addition to monitoring therm as an input, the adt7467 can optionally drive therm low as an output. in cases where prochot is bidirectional, therm can be used to throttle the processor by asserting prochot . the user can preprogram system-critical thermal limits. if the temperature exceeds a thermal limit by 0.25c, therm asserts low. if the temperature is still above the thermal limit on the next monitoring cycle, therm stays low. therm remains asserted low until the temperature is equal to or below the thermal limit. because the temperature for that channel is measured only once for every monitoring cycle, after therm asserts it is guaranteed to remain low for at least one monitoring cycle. the therm pin can be configured to assert low, if the remote 1, local, or remote 2 therm temperature limits are exceeded by 0.25c. the therm temperature limit registers are at registers 0x6a, 0x6b, and 0x6c, respectively. setting bit 3 of registers 0x5f, 0x60, and 0x61 enables the therm output feature for the remote 1, local, and remote 2 temperature channels, respectively. figure 33 shows how the therm pin asserts low as an output in the event of a critical overtemperature. adt7467 monitoring cycle temp therm limit +0.25c therm 04498-0-027 therm limit figure 33. asserting therm as an output, based on tripping therm limits an alternative method of disabling therm is to program the therm temperature limit to C64c or less in offset 64 mode, or ?128c or less in twos complement mode; that is, for therm temperature limit values less than C63c or C128c, respectively, therm is disabled.
adt7467 rev. 0 | page 26 of 80 fan drive using pwm control the adt7467 uses pulse-width modulation (pwm) to control fan speed. this relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. the external circuitry required to drive a fan using pwm control is extremely simple. for 4-wire fans, the pwm drive might need only a pull-up resistor. in many cases, the 4-wire fan pwm input has a built-in pull-up resistor. the adt7467 pwm frequency can be set to a selection of low frequencies or a single high pwm frequency. the low frequency options are usually used for 2-wire and 3-wire fans, while the high frequency option us usuall y used with 4-wire fans. for 2-wire or 3-wire fans, a single n-channel mosfet is the only drive device required. the specifications of the mosfet depend on the maximum current required by the fan being driven. typical notebook fans draw a nominal 170 ma, and so sot devices can be used where board space is a concern. in desktops, fans can typically draw 250 ma to 300 ma each. if you drive several fans in parallel from a single pwm output or drive larger server fans, the mosfet must handle the higher current requirements. the only other stipulation is that the mosfet should have a gate voltage drive, v gs < 3.3 v, for direct interfacing to the pwm_out pin. v gs can be greater than 3.3 v as long as the pull-up on the gate is tied to 5 v. the mosfet should also have a low on resistance to ensure that there is not significant voltage drop across the fet, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. figure 34 shows how to drive a 3-wire fan using pwm control. adt7467 tach/ain pwm 12v fan q1 ndt3055l 3.3v 12v 12v 10k ? 4.7k ? 10k ? 10k ? 1n4148 04498-0-028 figure 34. driving a 3-wire fan using an n-channel mosfet figure 34 uses a 10 k ? pull-up resistor for the tach signal. this assumes that the tach signal is an open-collector from the fan. in all cases, the tach signal from the fan must be kept below 5 v maximum to prevent damaging the adt7467. if in doubt as to whether the fan used has an open-collector or totem pole tach output, use one of the input signal conditioning circuits shown in the fan speed measurement section. figure 35 shows a fan drive circuit using an npn transistor such as a general-purpose mmbt2222. while these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than mosfets. when choosing a transistor, care should be taken to ensure that it meets the fans current requirements. ensure that the base resistor is chosen such that the transistor is saturated when the fan is powered on. because 4-wire fans are powered continuously, the fan speed is not switched on or off as with previous pwm driven/powered fans. this enables it to perform better than 3-wire fans, especially for high frequency applications. figure 36 shows a typical drive circuit for 4-wire fans. adt7467 tach tach pwm 12v fan q1 mmbt2222 3.3v 12v 12v 665 ? 4.7k ? 10k ? 10k ? 1n4148 04498-0-029 figure 35. driving a 3-wire fan using an npn transistor 04498-0-041 adt7467 tach/ain pwm 12v, 4-wire fan 3.3v 12v 12v 2k ? 4.7k ? 10k ? 10k ? v cc tach tach pwm figure 36. driving a 4-wire fan driving two fans from pwm3 the adt7467 has four tach inputs available for fan speed measurement, but only three pwm drive outputs. if a fourth fan is being used in the system, it should be driven from the pwm3 output in parallel with the third fan. figure 37 shows how to drive two fans in parallel using low cost npn transistors. figure 38 shows the equivalent circuit using a mosfet.
adt7467 rev. 0| page 27 of 80 adt7467 pwm3 3.3v 3.3v 12v 04498-0-030 1n4148 q1 mmbt3904 q2 mmbt2222 q3 mmbt2222 10 ? 10 ? 2.2k ? 1k ? tach3 tach4 figure 37. interfacing two fans in parallel to the pwm3 output using low cost npn transistors adt7467 pwm3 tach3 tach4 3.3v 3.3v 3.3v 04498-0-031 +v +v tach tach q1 ndt3055l 1n4148 5v or 12v fan 5v or 12v fan 10k ? typical 10k ? typical 10k ? typical figure 38. interfacing two fans in parallel to the pwm3 output using a single n-channel mosfet because the mosfet can handle up to 3.5 a, it is simply a matter of connecting another fan directly in parallel with the first. care should be taken in designing drive circuits with transistors and fets to ensure that the pwm pins are not required to source current and that they sink less than the 5 ma maximum current specified on the data sheet. driving up to three fans from pwm3 tach measurements for fans are synchronized to particular pwm channels, for example, tach1 is synchronized to pwm1. tach3 and tach4 are both synchronized to pwm3, so pwm3 can drive two fans. alternatively, pwm3 can be pro- grammed to synchronize tach2, tach3, and tach4 to the pwm3 output. this allows pwm3 to drive two or three fans. in this case, the drive circuitry looks the same, as shown in figure 37 and figure 38. the sync bit in register 0x62 enables this function. synchronization is not required in high frequency mode when used with 4-wire fans. <4> (sync) enhance acoustics register 1 (reg. 0x62) sync = 1 , synchronizes tach2, tach3, and tach4 to pwm3. driving 2-wire fans the adt7467 can support 2-wire fans only when low fre- quency pwm mode is selected in configuration register 5, bit 2. if this bit is not set to 1, the adt7467 cannot measure the speed of 2-wire fans. figure 39 shows how a 2-wire fan can be connected to the adt7467. this circuit allows the speed of a 2-wire fan to be measured, even though the fan has no dedicated tach signal. a series resistor, r sense , in the fan circuit converts the fan commutation pulses into a voltage, which is ac-coupled into the adt7467 through the 0.01 f capacitor. on-chip signal conditioning allows accurate monitoring of fan speed. the value of r sense chosen depends upon the programmed input threshold and the current drawn by the fan. for fans drawing approximately 200 ma, a 2 ? r sense value is suitable when the threshold is programmed as 40 mv. for fans that draw more current, such as larger desktop or server fans, r sense can be reduced for the same programmed threshold. the smaller the threshold programmed the better, because more voltage is developed across the fan and the fan spins faster. figure 40 shows a typical plot of the sensing waveform at the tach/ain pin.
adt7467 rev. 0 | page 28 of 80 note that when the voltage spikes (either negative going or positive going) are more than 40 mv in amplitude, the fan speed can be reliably determined. 04498-0-032 adt7467 pwm tach 5v or 12v fan q1 ndt3055l 3.3v +v 10k ? typical 1n4148 0.01 f r sense 2 ? typical figure 39. driving a 2-wire fan 04498-0-033 figure 40. fan speed sensing waveform at tach/ain pin laying out 2-wire and 3-wire fans figure 41 shows how to lay out a common circuit arrangement for 2-wire and 3-wire fans. some components are not populated, depending on whether a 2-wire or 3-wire fan is used. 04498-0-042 q1 mmbt2222 r2 r1 r3 r4 r5 pwm 1n4148 3.3v or 5v 12v or 5v c1 t ach for 3-wire fans: populate r1, r2, r3 r4 = 0w c1 = unpopulated for 2-wire fans: populate r4, c1 r1, r2, r3 unpopulated figure 41. planning for 2-wire or 3-wire fans on a pcb tach inputs pins 4, 6, 7, and 9 (when configured as tach inputs) are open- drain tach inputs intended for fan speed measurement. signal conditioning in the adt7467 accommodates the slow rise and fall times typical of fan tachometer outputs. the maximum input signal range is 0 v to 5 v, even when v cc is less than 5 v. in the event that these inputs are supplied from fan outputs that exceed 0 v to 5 v, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 42 to figure 45 show circuits for most common fan tach outputs. if the fan tach output has a resistive pull-up to v cc , it can be connected directly to the fan input, as shown in figure 42. 12v v cc 04498-0-034 pull-up 4.7k ? typical tach output fan speed counter tach adt7467 figure 42. fan with tach pull-up to v cc if the fan output has a resistive pull-up to 12 v (or other voltage greater than 5 v) then the fan output can be clamped with a zener diode, as shown in figure 43. the zener diode voltage should be chosen so that it is greater than v ih of the tach input but less than 5 v, allowing for the voltage tolerance of the zener. a value of between 3 v and 5 v is suitable. 12v v cc 04498-0-035 pull-up 4.7k ? typical tach output fan speed counter tach adt7467 zd1* *choose zd1 voltage approximately 0.8 v cc figure 43. fan with tach pull-up to voltage > 5 v. (for example, 12 v) clamped with zener diode if the fan has a strong pull-up (less than 1 k ? ) to 12 v or a totem-pole output, then a series resistor can be added to limit the zener current, as shown in figure 44.
adt7467 rev. 0| page 29 of 80 5v or 12v v cc 04498-0-036 pull-up typ <1k ? or totem pole tach output fan speed counter tach adt7467 zd1 zener* fan *choose zd1 voltage approximately 0.8 v cc r1 10k ? figure 44. fan with strong tach pull-up to > v cc or totem-pole output, clamped with zener and resistor alternatively, a resistive attenuator can be used, as shown in figure 45. r1 and r2 should be chosen such that 2 v < v pull-up r2 /( r pull-up + r1 + r2 ) < 5 v the fan inputs have an input resistance of nominally 160 k ? to ground, which should be taken into account when calculating resistor values. with a pull-up voltage of 12 v and pull-up resistor less than 1 k?, suitable values for r1 and r2 would be 100 k? and 47 k?, respectively. this gives a high input voltage of 3.83 v. 12v v cc 04498-0-037 <1k ? tach output fan speed counter tach adt7467 r2* *see text r1* figure 45. fan with strong tach pull-up to > v cc or totem-pole output, attenuated with r1/r2 fan speed measurement the fan counter does not count the fan tach output pulses directly, because the fan speed could be less than 1,000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on-chip 90 khz oscillator into the input of a 16-bit counter for n periods of the fan tach output (figure 46), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. n , the number of pulses counted, is determined by the settings of register 0x7b (tach pulses per revolution register). this register contains two bits for each fan, allowing one, two (default), three, or four tach pulses to be counted. 1 2 3 4 c loc k pwm tach 04498-0-038 figure 46. fan speed measurement fan speed measurement registers the fan tachometer readings are 16-bit values consisting of a 2- byte read from the adt7467. reg. 0x28 tach1 l ow byte = 0x00 default reg. 0x29 tach1 high byte = 0x00 default reg. 0x2a tach2 l ow byte = 0x00 default reg. 0x2b tach2 high byte = 0x00 default reg. 0x2c tach3 l ow byte = 0x00 default reg. 0x2d tach3 high byte = 0x00 default reg. 0x2e tach4 l ow byte = 0x00 default reg. 0x2f tach4 high byte = 0x00 default reading fan speed from the adt7467 the measurement of fan speeds involves a 2-register read for each measurement. the low byte should be read first. this causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous tach readings. the fan tachometer reading registers report back the number of 11.11 s period clocks (90 khz oscillator) gated to the fan speed counter, from the rising edge of the first fan tach pulse to the rising edge of the third fan tach pulse (assuming two pulses per revolution are being counted). because the device is essentially measuring the fan tach period, the higher the count value, the slower the fan is actually running. a 16-bit fan tachometer reading of 0xffff indicates either that the fan has stalled or is running very slowly (<100 rpm). high limit: > comparison performed because the actual fan tach period is being measured, falling below a fan tach limit by 1 sets the appropriate status bit and can be used to generate an smbalert .
adt7467 rev. 0 | page 30 of 80 fan tach limit registers the fan tach limit registers are 16-bit values consisting of two bytes. reg. 0x54 tach1 minimum l ow byte = 0xff default reg. 0x55 tach1 minimum high byte = 0xff default reg. 0x56 tach2 minimum l ow byte = 0xff default reg. 0x57 tach2 minimum high byte = 0xff default reg. 0x58 tach3 minimum l ow byte = 0xff default reg. 0x59 tach3 minimum high byte = 0xff default reg. 0x5a tach4 minimum l ow byte = 0xff default reg. 0x5b tach4 minimum high byte = 0xff default fan speed measurement rate the fan tach readings are normally updated once every second. the fast bit (bit 3) of configuration register 3 (reg. 0x78), when set, updates the fan tach readings every 250 ms. if any of the fans are not being driven by a pwm channel but are powered directly from 5 v or 12 v, their associated dc bit in configuration register 3 should be set. this allows tach readings to be taken on a continuous basis for fans connected directly to a dc source. for optimal results, the associated dc bit should always be set when using 4-wire fans. calculating fan speed assuming a fan with a two pulses per revolution (and two pulses per revolution being measured) fan speed is calculated by fan speed (rpm) = (90,000 60)/ fan tach reading where fan tach reading is the 16-bit fan tachometer reading. example: tach1 high byte (reg. 0x29) = 0x17 tach1 low byte (reg. 0x28) = 0xff what is fan 1 speed in rpm? fan 1 tach reading = 0x17ff = 6143 (decimal) rpm = (f 60)/fan 1 tach reading rpm = (90000 60)/6143 fan speed = 879 rpm fan pulses per revolution different fan models can output either 1, 2, 3, or 4 tach pulses per revolution. once the number of fan tach pulses has been determined, it can be programmed into the fan pulses per revolution register (reg. 0x7b) for each fan. alternatively, this register can be used to determine the number or pulses per revolution output by a given fan. by plotting fan speed measure- ments at 100% speed with different pulses per revolution setting, the smoothest graph with the lowest ripple determines the correct pulses per revolution value. fan pulses per revolution register <1:0> fan 1 default = 2 pulses per revolution. <3:2> fan 2 default = 2 pulses per revolution. <5:4> fan 3 default = 2 pulses per revolution. <7:6> fan 4 default = 2 pulses per revolution. 00 = 1 pulse per revolution. 01 = 2 pulses per revolution. 10 = 3 pulses per revolution. 11 = 4 pulses per revolution. 2-wire fan speed measurements (low frequency mode only) the adt7467 is capable of measuring the speed of 2-wire fans, that is, fans without tach outputs. to do this, the fan must be interfaced as shown in the driving 2-wire fans section. in this case, the tach inputs should be reprogrammed as analog inputs, ain. configuration register 2 (reg. 0x73) bit 3 (ain4) = 1, pin 9 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. bit 2 (ain3) = 1, pin 4 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. bit 1 (ain2) = 1, pin 7 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. bit 0 (ain1) = 1, pin 6 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. ain switching threshold having configured the tach inputs as ain inputs for 2-wire measurements, a user can select the sensing threshold for the ain signal.
adt7467 rev. 0| page 31 of 80 configuration register 4 (reg. 0x7d) <3:2> ainl, input threshold for 2-wire fan speed measurements. 00 = 20 mv 01 = 40 mv 10 = 80 mv 11 = 130 mv fan spin-up the adt7467 has a unique fan sp in-up function. it spins the fan at 100% pwm duty cycle until two tach pulses are de- tected on the tach input. once two tach pulses have been detected, the pwm duty cycle goes to the expected running value, for example, 33%. the advantage is that fans have different spin-up characteristics and take different times to overcome inertia. the adt7467 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans pro- grammed to spin up for a given spin-up time. fan startup timeout to prevent the generation of false interrupts as a fan spins up (because it is below running speed), the adt7467 includes a fan startup timeout function. during this time, the adt7467 looks for two tach pulses. if two tach pulses are not detected, then an interrupt is generated. using configuration register 4 (0x40) bit 5 (fspdis), this functionality can be changed (see the disabling fan startup timeout section). pwm1 configuration (reg. 0x5c) <2:0> spin , startup timeout for pwm1. 000 = no startup timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 s 110 = 2 s 111 = 4 s pwm2 configuration (reg. 0x5d) <2:0> spin, startup timeout for pwm2. 000 = no startup timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 s 110 = 2 s 111 = 4 s pwm3 configuration (reg. 0x5e) <2:0> spin , start-up timeout for pwm3. 000 = no startup timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 s 110 = 2 s 111 = 4 s disabling fan startup timeout although fan startup makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. setting bit 5 (fspdis) to 1 in configuration register 1 (reg. 0x40) disables the spin-up for two tach pulses. instead, the fan spins up for the fixed time as selected in reg. 0x5c to reg. 0x5e. pwm logic state the pwm outputs can be programmed high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted). pwm1 configuration (reg. 0x5c) <4> inv. 0 = logic high for 100% pwm duty cycle. 1 = logic low for 100% pwm duty cycle. pwm2 configuration (reg. 0x5d) <4> inv . 0 = logic high for 100% pwm duty cycle. 1 = logic low for 100% pwm duty cycle. pwm3 configuration (reg. 0x5e) <4> inv . 0 = logic high for 100% pwm duty cycle. 1 = logic low for 100% pwm duty cycle. low frequency mode pwm drive frequency the pwm drive frequency can be adjusted for the application. reg. 0x5f to reg. 0x61 configure the pwm frequency for pwm1 to pwm3, respectively. in high frequency mode, the pwm drive frequency is always 22.5 khz and cannot be changed.
adt7467 rev. 0 | page 32 of 80 pwm1 frequency registers (reg. 0x5f to reg. 0x61) <2:0> freq . 000 = 11.0 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz default 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz fan speed control the adt7467 controls fan speed using two modes: automatic and manual. in automatic fan speed control mode, fan speed is automatically varied with temperature and without cpu intervention, once initial parameters are set up. the advantage of this is that, if the system hangs, the user is guaranteed that the system is protected from overheating. the automatic fan speed control incorporates a feature called dynamic t min calibration. this feature reduces the design effort required to program the automatic fan speed control loop. for more information and how to program the automatic fan speed control loop and dynamic t min calibration, see the programming the automatic fan speed control loop section. in manual fan speed control mode, the adt7467 allows the duty cycle of any pwm output to be manually adjusted. this can be useful, if the user wants to change fan speed in software or adjust pwm duty cycle output for test purposes. bits <7:5> of reg. 0x5c to reg. 0x5e (pwm configuration) control the behavior of each pwm output. pwm configuration register (reg. 0x5c to reg. 0x5e) <7:5> bhvr. 111 = manual mode. once under manual control, each pwm output can be manually updated by writing to reg. 0x30 to reg. 0x32 (pwmx current duty cycle registers). programming the pwm current duty cycle registers the pwm current duty cycle registers are 8-bit registers that allow the pwm duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%. the value to be programmed into the pwm min register is given by value (decimal) = pwm min /0.39 example 1 : for a pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 0x80 (hex) example 2 : for a pwm duty cycle of 33%, value (decimal) = 33/0.39 = 85 (decimal) value = 85 (decimal) or 0x54 (hex) pwm duty cycle registers reg. 0x30 pwm1 duty cycle = 0x00 (0% default) reg. 0x31 pwm2 duty cycle = 0x00 (0% default) reg. 0x32 pwm3 duty cycle = 0x00 (0% default) by reading the pwmx current duty cycle registers, the user can keep track of the current duty cycle on each pwm output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. see the programming the automatic fan speed control loop section for details. operating from 3.3 v standby the adt7467 has been specifically designed to operate from a 3.3 v stby supply. in computers that support s3 and s5 states, the core voltage of the processor is lowered in these states. if using the dynamic t min mode, lowering the core voltage of the processor changes the cpu temperature and changes the dynamics of the system under dynamic t min control. likewise, when monitoring therm , the therm timer should be disabled during these states. dynamic tmin control register 1 (reg. 0x36) <1> vccplo = 1 when the power is supplied from 3.3 v stby and the v ccp voltage drops below the v ccp low limit, the following occurs: 1. status bit 1 (v ccp ) in status register 1 is set. 2. smbalert is generated if enabled. 3. therm monitoring is disabled. the therm timer should hold its value prior to the s3 or s5 state. 4. dynamic t min control is disabled. this prevents t min from being adjusted due to an s3 or s5 state. 5. the adt7467 is prevented from entering the shutdown state. once the core voltage, v ccp , goes above the v ccp low limit, everything is re-enabled and the system resumes normal operation.
adt7467 rev. 0| page 33 of 80 xnor tree test mode the adt7467 includes an xnor tr ee test mode. this mode is useful for in-circuit test equipment at board-level testing. by applying stimulus to the pins included in the xnor tree, it is possible to detect opens or shorts on the system board. figure 47 shows the signals that are exercised in the xnor tree test mode. the xnor tree test is invoked by setting bit 0 (xen) of the xnor tree test enable register (reg. 0x6f). pwm1/xto pwm3 pwm2 tach 4 tach3 tach2 tach1 04498-0-040 figure 47. xnor tree test power-on default when the adt7467 is powered up, it polls the v ccp input. if v ccp stays below 0.75 v (the system cpu power rail is not powered up), then the adt7467 assumes the functionality of the default registers after the adt7467 is addressed via any valid smbus transaction. if v cc goes high (the system processor power rail is powered up), then a fail-safe timer begins to count down. if the adt7467 is not addressed by any valid smbus transaction before the fail- safe timeout (4.6 s) lapses, then the adt7467 drives the fans to full speed. if the adt7467 is addressed by a valid smbus transaction after this point, the fans stop, and the adt7467 assumes its default settings and begins normal operation. if v ccp goes high (the system processor power rail is powered up), then a fail-safe timer begins to count down. if the adt7467 is addressed by a valid smbus transaction before the fail-safe timeout (4.6 s) lapses, then the adt7467 operates normally, assuming the functionality of all the default registers. see the flow chart in figure 48. adt7467 is powered up has the adt7467 been accessed by a valid smbus transaction? is v ccp above 0.75v? check v ccp start fail-safe timer has the adt7467 been accessed by a valid smbus transaction? fail-safe timer elapses after the fail-safe timeout has the adt7467 been accessed by a valid smbus transaction? start up the adt7467 normally run the fans to full speed has the adt7467 been accessed by a valid smbus transaction? switch off fans n n n n n y y y y y 04498-0-043 figure 48. power-on flow chart
adt7467 rev. 0 | page 34 of 80 programming the automatic fan speed control loop note: to more efficiently understand the automatic fan speed control loop, it is strongly recommended to use the adt7467 evaluation board and software while reading this section. this section provides the system designer with an understand- ing of the automatic fan control loop, and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. to optimize the system characteristics, the designer needs to give some thought to system configuration, including the number of fans, where they are located, and what tempera- tures are being measured in the particular system. the mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of the process. automatic fan control overview the adt7467 can automatically control the speed of fans based upon the measured temperature. this is done independently of cpu intervention once initial parameters are set up. the adt7467 has a local temperature sensor and two remote temperature channels that can be connected to a cpu on-chip thermal diode (available on intel pentium class and other cpus). these three temperature channels can be used as the basis for automatic fan speed control to drive fans using pulse- width modulation (pwm). automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. reducing fan speed can also decrease system current consumption. the automatic fan speed control mode is very flexible owing to the number of programmable parameters, including t min and t range . the t min and t range values for a temperature channel and, therefore, for a given fan are critical, because they define the thermal characteristics of the system. the thermal validation of the system is one of the most important steps in the design process, so these values should be selected carefully. figure 49 gives a top-level overview of the automatic fan control circuitry on the adt7467. from a systems-level perspective, up to three system temperatures can be monitored and used to control three pwm outputs. the three pwm outputs can be used to control up to four fans. the adt7467 allows the speed of four fans to be monitored. each temperature channel has a thermal calibration block, allowing the designer to individually configure the thermal characteristics of each temperature channel. for example, one can decide to run the cpu fan when cpu temperature increases above 60c and a chassis fan when the local temperature increases above 45c. at this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (pwm) channel. the right side of figure 49 shows controls that are fan-specific. the designer has individual control over parameters such as minimum pwm duty cycle, fan speed failure thresholds, and even ramp control of the pwm outputs. automatic fan control, then, ultimately allows graceful fan speed changes that are less perceptible to the system user. mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range remote 1 temp local temp remote 2 temp 04498-0-054 tachometer 1 measurement pwm config pwm min pwm1 ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min pwm2 ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min pwm3 ramp control (acoustic enhancement) pwm generator 100% tach1 tach2 tach3 figure 49. automatic fan control block diagram
adt7467 rev. 0| page 35 of 80 step 1: hardware configuration during system design, the motherboard sensing and control capabilities should be addressed early in the design stages. decisions about how these capabilities are used should involve the system thermal/mechanical engineer. ask the following questions: 1. what adt7467 functionality will be used? ? pwm2 or smbalert ? ? tach4 fan speed measurement or overtemperature therm function? ? 5 v voltage monitoring or overtemperature therm function? ? 12 v voltage monitoring or vid5 input? the adt7467 offers multifunctional pins that can be reconfigured to suit different system requirements and physical layouts. these multifunction pins are software programmable. 2. how many fans will be supported in system, three or four? this influences the choice of whether to use the tach4 pin or to reconfigure it for the therm function. 3. is the cpu fan to be controlled using the adt7467 or will it run at full speed 100% of the time? if run at 100%, this frees up a pwm output, but the system is louder. 4. where will the adt7467 be physically located in the system? this influences the assignment of the temperature measurement channels to particular system thermal zones. for example, locating the adt7467 close to the vrm controller circuitry allows the vrm temperature to be monitored using the local temperature channel. rear chassis front chassis cpu fan sink remote 1 = ambient temp local = vrm temp remote 2 = cpu temp 04499-0-055 pwm1 pwm2 tach1 tach2 tach3 pwm3 mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% figure 50. hardware configuration example
adt7467 rev. 0 | page 36 of 80 recommended implementation 1 configuring the adt7467 as in figure 51 provides the system designer with the following features: 1. six vid inputs (vid0 to vid5) for vrm10 support. 2. two pwm outputs for fan control of up to three fans. (the front and rear chassis fans are connected in parallel.) 3. three tach fan speed measurement inputs. 4. v cc measured internally through pin 4. 5. cpu core voltage measurement (v core ). 6. 2.5 v measurement input used to monitor cpu current (connected to v comp output of adp316x vrm controller). this is used to determine cpu power consumption. 7. 5 v measurement input. 8. vrm temperature using local temperature sensor. 9. cpu temperature measured using the remote 1 temperature channel. 10. ambient temperature measured through the remote 2 temperature channel. 11. if not using vid5, this pin can be reconfigured as the 12 v monitoring input. 12. bidirectional therm pin allows the monitoring of prochot output from an intel? p4 processor, for example, or can be used as an overtemperature therm output. 13. smbalert system interrupt output. cpu fan cpu ich front chassis fan tach2 adt7467 pwm3 rear chassis fan ambient temperature adp316x vrm controller v comp tach3 d1+ d1? 3.3vsb 5v 12v/vid5 current v core gnd pwm1 tach1 vid[0:4]/vid[0.5] d2+ d2? therm smbalert sda scl prochot 5(vrm9)/6(vrm10) 04498-0-056 figure 51. recommended implementation 1
adt7467 rev. 0| page 37 of 80 recommended implementation 2 configuring the adt7467 as in figure 52 provides the system designer with the following features: 1. six vid inputs (vid0 to vid5) for vrm10 support. 2. three pwm outputs for fan control of up to three fans. (all three fans can be individually controlled.) 3. three tach fan speed measurement inputs. 4. v cc measured internally through pin 4. 5. cpu core voltage measurement (v core ). 6. 2.5 v measurement input used to monitor cpu current (connected to v comp output of adp316x vrm controller). this is used to determine cpu power consumption. 7. 5 v measurement input. 8. vrm temperature using local temperature sensor. 9. cpu temperature measured using the remote 1 temperature channel. 10. ambient temperature measured through the remote 2 temperature channel. 11. if not using vid5, this pin can be reconfigured as the 12 v monitoring input. 12. bidirectional therm pin allows the monitoring of prochot output from an intel p4 processor, for example, or can be used as an overtemperature therm output. cpu fan cpu ich front chassis fan tach2 adt7467 pwm3 rear chassis fan ambient temperature adp316x vrm controller v comp tach3 d1+ d1? 3.3vsb 5v 12v/vid5 current v core gnd pwm1 tach1 vid[0:4]/vid[0.5] d2+ d2? therm sda scl prochot 5(vrm9)/6(vrm10) 04498-0-057 figure 52. recommended implementation 2
adt7467 rev. 0 | page 38 of 80 step 2: configuring the mux after the system hardware configuration is determined, the fans can be assigned to particular temperature channels. not only can fans be assigned to individual channels, but the behavior of the fans is also configurable. for example, fans can be run under automatic fan control, can be run manually (under software control), or can be run at the fastest speed calculated by multiple temperature channels. the mux is the bridge between temperature measurement channels and the three pwm outputs. bits <7:5> (bhvr) of registers 0x5c, 0x5d, and 0x5e (pwm configuration registers) control the behavior of the fans connected to the pwm1, pwm2, and pwm3 outputs. the values selected for these bits determine how the mux connects a temperature measurement channel to a pwm output. automatic fan control mux options <7:5> (bhvr), registers 0x5c, 0x5d, 0x5e. 000 = remote 1 temperature controls pwmx 001 = local temperature controls pwmx 010 = remote 2 temperature controls pwmx 101 = fastest speed calculated by local and remote 2 temperature controls pwmx 110 = fastest speed calculated by all three temperature channels controls pwmx the fastest speed calculated options pertain to controlling one pwm output based on multiple temperature channels. the thermal characteristics of the three temperature zones can be set to drive a single fan. an example would be the fan turning on when remote 1 temperature exceeds 60c or if the local temperature exceeds 45c. other mux options <7:5> (bhvr), registers 0x5c, 0x5d, 0x5e. 011 = pwmx runs full speed 100 = pwmx disabled (default) 111 = manual mode. pwmx is runner under software control. in this mode, pwm duty cycle registers (registers 0x30 to 0x32) are writable and control the pwm outputs. mux 04498-0-058 rear chassis front chassis cpu fan sink remote 1 = ambient temp local = vrm temp remote 2 = cpu temp pwm1 pwm2 tach1 tach2 tach3 pwm3 mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% figure 53. assigning temperature channels to fan channels
adt7467 rev. 0| page 39 of 80 mux configuration example this is an example of how to configure the mux in a system using the adt7467 to control three fans. the cpu fan sink is controlled by pwm1, the front chassis fan is controlled by pwm2, and the rear chassis fan is controlled by pwm3. the mux is configured for the following fan control behavior: ? pwm1 (cpu fan sink) is controlled by the fastest speed calculated by the local (vrm temperature) and remote 2 (processor) temperature. in this case, the cpu fan sink is also being used to cool the vrm. ? pwm2 (front chassis fan) is controlled by the remote 1 temperature (ambient). ? pwm3 (rear chassis fan) is controlled by the remote 1 temperature (ambient). example mux settings <7:5> (bhvr), pwm1 configuration register 0x5c. 101 = fastest speed calculated by local and remote 2 temperature controls pwm1 <7:5> (bhvr), pwm2 configuration register 0x5d. 000 = remote 1 temperature controls pwm2 <7:5> (bhvr), pwm3 configuration register 0x5e. 000 = remote 1 temperature controls pwm3 these settings configure the mux, as shown in figure 54. 04498-0-059 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% mux figure 54. mux configuration example
adt7467 rev. 0 | page 40 of 80 step 3: t min settings for thermal calibration channels t min is the temperature at which the fans start to turn on under automatic fan control. the speed at which the fan runs at t min is programmed later. the t min values chosen are temperature channel specific, for example, 25c for ambient channel, 30c for vrm temperature, and 40c for processor temperature. t min is an 8-bit value, either twos complement or offset 64, that can be programmed in 1c increments. there is a t min register associated with each temperature measurement channel: remote 1 local, and remote 2 temp. once the t min value is exceeded, the fan turns on and runs at the minimum pwm duty cycle. the fan turns off once the temperature has dropped below t min C t hyst . to overcome fan inertia, the fan is spun up until two valid tach rising edges are counted. see the fan startup timeout section for more details. in some cases, primarily for psycho- acoustic reasons, it is desirable that the fan never switch off below t min . bits <7:5> of enhanced acoustics register 1 (reg. 0x62), when set, keep the fans running at the pwm minimum duty cycle, if the temperature should fall below t min . t min registers reg. 0x67, remote 1 temperature t min = 0x9a (90c) reg. 0x68, local temperature t min = 0x9a (90c) reg. 0x69, remote 2 temperature t min = 0x9a (90c) enhance acoustics register 1 (reg. 0x62) bit 7 (min3) = 0, pwm3 is off (0% pwm duty cycle) when temperature is below t min C t hyst . bit 7 (min3) = 1, pwm3 runs at pwm3 minimum duty cycle below t min C t hyst . bit 6 (min2) = 0, pwm2 is off (0% pwm duty cycle) when temperature is below t min C t hyst . bit 6 (min2) = 1, pwm2 runs at pwm2 minimum duty cycle below t min C t hyst . bit 5 (min1) = 0, pwm1 is off (0% pwm duty cycle) when temperature is below t min C t hyst . bit 5 (min1) = 1, pwm1 runs at pwm1 minimum duty cycle below t min C t hyst . 04498-0-060 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% 0% 100% p w m d u t y c y c l e t min figure 55. understanding the t min parameter
adt7467 rev. 0| page 41 of 80 step 4: pwm min for each pwm (fan) output pwm min is the minimum pwm duty cycle at which each fan in the system runs. it is also the start speed for each fan under automatic fan control once the temperature rises above t min . for maximum system acoustic benefit, pwm min should be as low as possible. depending on the fan used, the pwm min setting is usually in the 20% to 33% duty cycle range. this value can be found through fan validation. temperature t min 100% pwm min 0% pwm duty cycle 04498-0-061 figure 56. pwm min determines minimum pwm duty cycle more than one pwm output can be controlled from a single temperature measurement channel. for example, remote 1 temperature can control pwm1 and pwm2 outputs. if two different fans are used on pwm1 and pwm2, then the fan characteristics can be set up differently. as a result, fan 1 driven by pwm1 can have a different pwm min value than that of fan 2 connected to pwm2. figure 57 illustrates this as pwm1 min (front fan) is turned on at a minimum duty cycle of 20%, while pwm2 min (rear fan) turns on at a minimum of 40% duty cycle. note, however, that both fans turn on at exactly the same temperature, defined by t min . temperature t min 100% pwm1 min 0% pwm duty cycle p w m 1 p w m 2 pwm2 min 04498-0-062 figure 57. operating two different fans from a single temperature channel programming the pwm min registers the pwm min registers are 8-bit registers that allow the minimum pwm duty cycle for each output to be configured anywhere from 0% to 100%. this allows the minimum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm min register is given by value (decimal) = pwm min /0.39 example 1: for a minimum pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 80 (hex) example 2: for a minimum pwm duty cycle of 33%, value (decimal) = 33/0.39 = 85 (decimal) value = 85 (decimal)l or 54 (hex) pwm min registers reg. 0x64, pwm1 minimum duty cycle = 0x80 (50% default) reg. 0x65 pwm2 minimum duty cycle = 0x80 (50% default) reg. 0x66, pwm3 minimum duty cycle = 0x80 (50% default) note on fan speed and pwm duty cycle the pwm duty cycle does not directly correlate to fan speed in rpm. running a fan at 33% pwm duty cycle does not equate to running the fan at 33% speed. driving a fan at 33% pwm duty cycle actually runs the fan at closer to 50% of its full speed. this is because fan speed in %rpm generally relates to the square root of pwm duty cycle. given a pwm square wave as the drive signal, fan speed in rpm approximates to 10 % = cycle duty pwm fanspeed step 5: pwm max for pwm (fan) outputs pwm max is the maximum duty cycle that each fan in the system runs at under the automatic fan speed control loop. for maximum system acoustic benefit, pwm max should be as low as possible, but should be capable of maintaining the processor temperature limit at an acceptable level. if the therm temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling. there is a pwm max limit for each fan channel. the default value of this register is 0xff and so has no effect unless it is programmed.
adt7467 rev. 0 | page 42 of 80 temperature t min 100% pwm min 0% pwm duty cycle pwm max 04498-0-063 figure 58. pwm max determines maximum pwm duty cycle below the therm temperature limit programming the pwm max registers the pwm max registers are 8-bit registers that allow the maximum pwm duty cycle for each output to be configured anywhere from 0% to 100%. this allows the maximum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm max register is given by value (decimal) = pwm max /0.39 example 1: for a maximum pwm duty cycle of 50%, value (decimal) C 50/0.39 = 128 (decimal) value = 128 (decimal) or 80 (hex) example 2: for a minimum pwm duty cycle of 75%, value (decimal) = 75/0.39 = 85 (decimal) value = 192 (decimal) or c0 (hex) pwm max registers reg. 0x38, pwm1 maximum duty cycle = 0xff (100% default) reg. 0x39, pwm2 maximum duty cycle = 0xff (100% default) reg. 0x3a, pwm3 maximum duty cycle = 0xff (100% default) see the note on fan speed and pwm duty cycle on page 41. step 6: t range for temperature channels t range is the range of temperature over which automatic fan control occurs once the programmed t min temperature has been exceeded. t range is a temperature slope, not an arbitrary value, that is, a t range of 40c holds true only for pwm min = 33%. if pwm min is increased or decreased, the effective t range changes. temperature t min 100% pwm min 0% pwm duty cycle t range 04498-0-064 figure 59. t range parameter affects cooling slope the t range or fan control slope is determined by the following procedure: 1. determine the maximum operating temperature for that channel (for example, 70c). 2. determine experimentally the fan speed (pwm duty cycle value) that does not exceed the temperature at the worst- case operating points. (for example, 70c is reached when the fans are running at 50% pwm duty cycle.) 3. determine the slope of the required control loop to meet these requirements. 4. using the adt7467 evaluation software, can graphically program and visualize this functionality. ask your local analog devices representative for details. t min 100% 33% 0% pwm duty cycle 50% 30c 40c 04498-0-065 figure 60. adjusting pwm min affects t range
adt7467 rev. 0| page 43 of 80 t range is implemented as a slope, which means that as pwm min is changed, t range changes, but the actual slope remains the same. the higher the pwm min value, the smaller the effective t range , that is, the fan reaches full speed (100%) at a lower temperature. t min 100% 33% 0% pwm duty cycle 50% 30c 40c 25% 10% 45c 54c 04498-0-066 figure 61. increasing pwm min changes effective t range for a given t range value, the temperature at which the fan runs at full speed for different pwm min values can be easily calculated: t max = t min + ( max dc ? min dc ) t range /170 where: t max is the temperature at which the fan runs full speed. t min is the temperature at which the fan turns on. max dc is the maximum duty cycle (100%) = 255 decimal. min dc is equal to pwm min . t range is the duty pwm duty cycle vs. temperature slope. example: calculate t , given that t min = 30c, t range = 40c, and pwm min = 10% duty cycle = 26 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 10%) 40c/170 t max = 30c + (255 ? 26) 40c/170 t max = 84c ( effective t range = 54c) example: calculate t max , given that t min = 30c, t range = 40c, and pwm min = 25% duty cycle = 64 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 25%) 40c/170 t max = 30c + (255 ? 64) 40c/170 t max = 75c ( effective t range = 45c) example: calculate t max , given that t min = 30c, t range = 40c, and pwm min = 33% duty cycle = 85 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 33%) 40c/170 t max = 30c + (255 ? 85) 40c/170 t max = 70c ( effective t range = 40c) example: calculate t max , given that t min = 30c, t range = 40c, and pwm min = 50% duty cycle = 128 (decimal). t max = t min + ( max dc ? min dc ) t range /170 t max = 30c + (100% ? 50%) 40c/170 t max = 30c + (255 ? 128) 40c/170 t max = 60c ( effective t range = 30c) selecting a t range slope the t range value can be selected for each temperature channel: remote 1, local, and remote 2 temperature. bits <7:4> (t range ) of registers 0x5f to 0x61 define the t range value for each temperature channel. table 13. selecting a t range value bits <7:4> 1 t range (c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 (default) 1101 40 1110 53.33 1111 80 1 register 0x5f configures remote 1 t range . register 0x60 configures local t range . register 0x61 configures remote 2 t range . summary of t range function when using the automatic fan control function, the temperature at which the fan reaches full speed can be calculated by t max = t min + t range (1) equation 1 holds true only when pwm min is equal to 33% pwm duty cycle.
adt7467 rev. 0 | page 44 of 80 increasing or decreasing pwm min changes the effective t range , although the fan control still follows the same pwm duty cycle to temperature slope. the effective t range for different pwm min values can be calculated using equation 2: t max = t min + ( max dc ? min dc ) t range /170 (2) where: ( max dc ? min dc ) t range /170 is the effective t range value. see the note on fan speed and pwm duty cycle. figure 62 shows pwm duty cycle versus temperature for each t range setting. the lower graph shows how each t range setting affects fan speed versus temperature. as can be seen from the graph, the effect on fan speed is nonlinear. temperature above t min 0 20406080100120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 temperature above t min 0 20 40 60 80 100 120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 04498-0-067 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c figure 62. t range vs. actual fan speed profile the graphs in figure 62 assume that the fan starts from 0% pwm duty cycle. clearly, the minimum pwm duty cycle, pwm min , needs to be factored in to see how the loop actually performs in the system. figure 63 shows how t range is affected when the pwm min value is set to 20%. it can be seen that the fan actually runs at about 45% fan speed when the temperature exceeds t min . temperature above t min 0 20 40 60 80 100 120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 temperature above t min 0 20 40 60 80 100 120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 04498-0-068 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c figure 63. t range and % fan speed slopes with pwm min = 20% example: determining t range for each temperature channel the following example shows how the different t min and t range settings can be applied to three different thermal zones. in this example, the following t range values apply: t range = 80c for ambient temperature t range = 53.3c for cpu temperature t range = 40c for vrm temperature this example uses the mux configuration described in step 2, with the adt7467 connected as shown in figure 54. both cpu temperature and vrm temperature drive the cpu fan connected to pwm1. ambient temperature drives the front chassis fan and rear chassis fan connected to pwm2 and pwm3. the front chassis fan is configured to run at pwm min = 20%. the rear chassis fan is configured to run at pwm min = 30%. the cpu fan is configured to run at pwm min = 10%. note on 4-wire fans the control range for 4-wire fans is much wider than that of 2 wire or 3 wire fans. in many cases, 4-wire fans can start with a pwm drive of as little as 20%.
adt7467 rev. 0| page 45 of 80 temperature above t min 0 10203040 100 50 60 70 80 90 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 temperature above t min 0 fan speed (% max rpm) 10 20 30 40 50 60 70 80 90 100 0 10203040 100 50 60 70 80 90 04498-0-069 figure 64. t range and % fan speed slopes for vrm, ambient, and cpu temperature channels step 7: t therm for temperature channels t therm is the absolute maximum temperature allowed on a temperature channel. above this temperature, a component such as the cpu or vrm might be operating beyond its safe operating limit. when the temperature measured exceeds t therm , all fans are driven at 100% pwm duty cycle (full speed) to provide critical system cooling. the fans remain running at 100% until the temperature drops below t therm minus hysteresis , where hysteresis is the number programmed into the hysteresis registers 0x6d and 0x6e. the default hysteresis value is 4c. the t therm limit should be considered the maximum worst-case operating temperature of the system. because exceeding any t therm limit runs all fans at 100%, it has very negative acoustic effects. ultimately, this limit should be set up as a fail-safe, and one should ensure that it is not exceeded under normal system operating conditions. note that the t therm limits are nonmaskable and affect the fan speed no matter how automatic fan control settings are configured. this allows some flexibility, because a t range value can be selected based on its slope, while a hard limit (such as 70c), can be programmed as t max (the temperature at which the fan reaches full speed) by setting t therm to that limit (for example, 70c). therm registers reg. 0x6a, remote 1 therm limit = 0xa4 (100c default) reg. 0x6b, local therm limit = 0xa4 (100c default) reg. 0x6c, remote 2 therm limit = 0xa4 (100c default) hysteresis registers reg. 0x6d, remote 1, local hysteresis register <7:4>, remote 1 temperature hysteresis (4c default). <3:0>, local temperature hysteresis (4c default). reg. 0x6e , remote 2 temperature hysteresis register <7:4>, remote 2 temperature hysteresis (4c default). because each hysteresis setting is four bits, hysteresis values are programmable from 1c to 15c. it is not recommended that hysteresis values ever be programmed to 0c, because this disables hysteresis. in effect, this would cause the fans to cycle between normal speed and 100% speed, creating unsettling acoustic noise.
adt7467 rev. 0 | page 46 of 80 04498-0-070 t min p w m d u t y c y c l e 0% 100% t therm t range rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% figure 65. how t therm relates to automatic fan control step 8: t hyst for temperature channels t hyst is the amount of extra cooling a fan provides after the temperature measured has dropped back below t min before the fan turns off. the premise for temperature hysteresis (t hyst ) is that, without it, the fan would merely chatter or cycle on and off regularly whenever temperature is hovering at about the t min setting. the t hyst value chosen determines the amount of time needed for the system to cool down or heat up as the fan is turning on and off. values of hysteresis are programmable in the range 1c to 15c. larger values of t hyst prevent the fans from chattering on and off. the t hyst default value is set at 4c. the t hyst setting applies not only to the temperature hysteresis for fan on/off, but the same setting is used for the t therm hysteresis value, described in step 6. therefore, programming registers 0x6d and 0x6e sets the hysteresis for both fan on/off and the therm function. hysteresis registers reg. 0x6d , remote 1, local hysteresis register <7:4>, remote 1 temperature hysteresis (4c default). <3:0>, local temperature hysteresis (4c default). reg. 0x6e , remote 2 temp hysteresis register <7:4>, remote 2 temperature hysteresis (4c default). in some applications, it is required that fans not turn off below t min , but remain running at pwm min . bits <7:5> of enhanced acoustics register 1 (reg. 0x62) allow the fans to be turned off or to be kept spinning below t min . if the fans are always on, the t hyst value has no effect on the fan when the temperature drops below t min .
adt7467 rev. 0| page 47 of 80 04498-0-071 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% t min p w m d u t y c y c l e 0% 100% t range t therm figure 66. the t hyst value applies to fan on/off hysteresis and therm hysteresis enhance acoustics register 1 (reg. 0x62) bit 7 (min3) = 0, pwm3 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 7 (min3) = 1, pwm3 runs at pwm3 minimum duty cycle below t min ? t hyst . bit 6 (min2) = 0, pwm2 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 6 (min2) = 1, pwm2 runs at pwm2 minimum duty cycle below t min ? t hyst . bit 5 (min1) = 0, pwm1 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 5 (min1) = 1, pwm1 runs at pwm1 minimum duty cycle below t min ? t hyst .
adt7467 rev. 0 | page 48 of 80 dynamic t min control mode in addition to the automatic fan speed control mode described in the automatic fan control overview section, the adt7467 has a mode that extends the basic automatic fan speed control loop. dynamic t min control allows the adt7467 to intelligently adapt the systems cooling solution for best system performance or lowest possible system acoustics, depending on user or design requirements. use of dynamic t min control alleviates the need to design for worst-case conditions and significantly reduces system design and validation time. designing for worst-case conditions system design must always allow for worst-case conditions. in pc design, the worst-case conditions include, but are not limited to the following: ? worst-c as e altitu de a computer can be operated at different altitudes. the altitude affects the relative air density, which alters the effectiveness of the fan cooling solution. for example, comparing 40c air temperature at 10,000 ft. to 20c air temperature at sea level, relative air density is increased by 40%. this means that the fan can spin 40% slower and make less noise at sea level than at 10,000 ft. while keeping the system at the same temperature at both locations. ? worst-c as e fan due to manufacturing tolerances, fan speeds in rpm are normally quoted with a tolerance of 20%. the designer needs to assume that the fan rpm can be 20% below tolerance. this translates to reduced system airflow and elevated system temperature. note that fans 20% out of tolerance can negatively impact system acoustics, because they run faster and generate more noise. ? worst-case chassis airflow the same motherboard can be used in a number of different chassis configurations. the design of the chassis and the physical location of fans and components determine the system thermal characteristics. moreover, for a given chassis, the addition of add-in cards, cables, or other system configuration options can alter the system airflow and reduce the effectiveness of the system cooling solution. the cooling solution can also be inadvertently altered by the end user. (for example, placing a computer against a wall can block the air ducts and reduce system airflow.) fan i/o cards poor cpu airflow vents power supply cpu drive bays good venting = good air exchange poor venting = poor air exchange 04498-0-072 vents fan i/o cards good cpu airflow fan vents power supply cpu drive bays figure 67. chassis airflow issues ? worst-case processor power consumption this data sheet maximum does not necessarily reflect the true processor power consumption. designing for worst- case cpu power consumption can result in a processor becoming overcooled (generating excess system noise). ? worst-case peripheral power consumption the tendency is to design to data sheet maximums for peripheral components (again overcooling the system). ? worst-case assembly every system manufactured is unique because of manufacturing variations. heat sinks may be loose fitting or slightly misaligned. too much or too little thermal grease might be used, or variations in application pressure for thermal interface material could affect the efficiency of the thermal solution. accounting for manufacturing variations in every system is difficult; therefore, the system must be designed for the worst case. substrate heat sink thermal interface material integrated heat spreader epoxy thermal interface material processor t a t j ca sa tims ctim timc jtim cs t c t tim t s t tim ja 04498-0-073 figure 68. thermal model although a design usually accounts for worst-case conditions in all these cases, the actual system is almost never operated at worst-case conditions. the alternative to designing for the worst case is to use the dynamic t min control function.
adt7467 rev. 0| page 49 of 80 dynamic t min control overview dynamic t min control mode builds upon the basic automatic fan control loop by adjusting the t min value based on system performance and measured temperature. this is important, because, instead of designing for the worst case, the system thermals can be defined as operating zones. adt7467 can self- adjust its fan control loop to maintain either an operating zone temperature or a system target temperature. for example, one can specify that the ambient temperature in a system should be maintained at 50c. if the temperature is below 50c, the fans might not need to run or might run very slowly. if the temperature is higher than 50c, the fans need to throttle up. the challenge presented by any thermal design is finding the right settings to suit the systems fan control solution. this can involve designing for the worst case, followed by weeks of system thermal characterization, and finally fan acoustic optimization (for psycho-acoustic reasons). getting the most benefit from the automatic fan control mode involves character- izing the system to find the best t min and t range settings for the control loop, and the best pwm min value for the quietest fan speed setting. using the adt7467s dynamic t min control mode, however, shortens the characterization time and alleviates tweaking the control loop settings, because the device can self- adjust during system operation. dynamic t min control mode is operated by specifying the operating zone temperatures required for the system. associated with this control mode are three operating point registers, one for each temperature channel. this allows the system thermal solution to be broken down into distinct thermal zones. for example, cpu operating temperature is 70c, vrm operating temperature is 80c, and ambient operating temperature is 50c. the adt7467 dynamically alters the control solution to maintain each zone temperature as closely as possible to its target operating point. operating point registers reg. 0x33, remote 1 operating point = 0xa4 (100c default) reg. 0x34, local operating point = 0xa4 (100c default) reg. 0x35, remote 2 operating point = 0xa4 (100c default) figure 69 shows an overview of the parameters that affect the operation of the dynamic t min control loop. pwm duty cycle t low t min operating point t high t range temperature 04498-0-074 t therm figure 69. dynamic t min control loop table 14 provides a brief description of each parameter. table 14. t min control loop parameters parameter description t low if the temperature drops below the t low limit, an error flag is set in a status register and an smbalert interrupt can be generated. t high if the temperature exceeds the t high limit, an error flag is set in a status register and an smbalert interrupt can be generated. t min the temperature at which the fan turns on under automatic fan speed control. operating point the target temperature for a particular temperature zone. the adt7467 attempts to maintain system temperature at about the operating point by adjusting the t min parameter of the control loop. t therm if the temperature exceeds this critical limit, the fans can be run at 100% for maximum cooling. t range programs the pwm duty cycle vs. temperature control slope. dynamic t min control programming because the dynamic t min control mode is a basic extension of the automatic fan control mode, program the automatic fan control mode parameters first, as described in step 1 to step 8, then proceed with dynamic t min control mode programming.
adt7467 rev. 0 | page 50 of 80 step 9: operating points for temperature channels the operating point for each temperature channel is the optimal temperature for that thermal zone. the hotter each zone is allowed to be, the quieter the system, because the fans are not required to run as fast. the ad t7467 increases or decreases fan speeds as necessary to maintain the operating point temperature, allowing for system-to-system variation and removing the need for worst-case design. if a sensible operating point value is chosen, any t min value can be selected in the system characterization. if the t min value is too low, the fans run sooner than required, and the temperature is below the operat- ing point. in response, the adt7467 increases t min to keep the fans off longer and to allow the temperature zone to get closer to the operating point. likewise, too high a t min value causes the operating point to be exce eded, and in turn, the adt7467 reduces t min to turn the fans on sooner to cool the system. programming operating point registers there are three operating point registers, one for each temperature channel. these 8-bit registers allow the operating point temperatures to be programmed with 1c resolution. operating point registers reg. 0x33, remote 1 operating point = 0xa4 (100c default) reg. 0x34, local operating point = 0xa4 (100c default) reg. 0x35, remote 2 operating poin t = 0xa4 (100c default) 04498-0-075 operating point rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% figure 70. operating point value dynamically adjusts automatic fan control settings
adt7467 rev. 0| page 51 of 80 step 10: high and low limits for temperature channels the low limit defines the temperature at which the t min value starts to be increased, if temperature falls below this value. this has the net effect of reducing the fan speed, allowing the system to get hotter. an interrupt can be generated when the tempera- ture drops below the low limit. the high limit defines the temperature at which the t min value starts to be reduced, if temperature increases above this value. this has the net effect of increasing fan speed to cool down the system. an interrupt can be generated when the temperature rises above the high limit. programming high and low limits there are six limit registers; a high limit and low limit are associated with each temperature channel. these 8-bit registers allow the high and low limit temperatures to be programmed with 1c resolution. temperature limit registers reg. 0x4e, remote 1 temperature low limit = 0x01 reg. 0x4f, remote 1 temperature high limit = 0x7f reg. 0x50, local temperature low limit = 0x01 reg. 0x51, local temperature high limit = 0x7f reg. 0x52, remote 2 temperature low limit = 0x01 reg. 0x53, remote 2 temperature high limit = 0x7f how dynamic t min control works the basic premise is as follows: 1. set the target temperature for the temperature zone, which could be, for example, the remote 1 thermal diode. this value is programmed to the remote 1 operating temperature register. 2. as the temperature in that zone (remote 1 temperature) rises toward and exceeds the operating point temperature, t min is reduced and the fan speed increases. 3. as the temperature drops below the operating point temperature, t min is increased and the fan speed is reduced. however, the loop operation is not as simple as described in these steps. a number of conditions govern the situations in which t min can increase or decrease. short cycle and long cycle the adt7467 implements two loops: a short cycle and a long cycle. the short cycle takes place every n monitoring cycles. the long cycle takes place every 2 n monitoring cycles. the value of n is programmable for each temperature channel. the bits are located at the following register locations: remote 1 = cyr1 = bits <2:0> of calibration control register 2 (address = 0x37). local = cyl = bits <5:3> of calibration control register 2 (address = 0x37). remote 2 = cyr2 = bits <7:6> of calibration control register 2 and bit 0 of calibration control register 1 (address = 0x36). table 15. cycle bit assignments code short cycle long cycle 000 8 cycles (1 s) 16 cycles (2 s) 001 16 cycles (2 s) 32 cycles (4 s) 010 32 cycles (4 s) 64 cycles (8 s) 011 64 cycles (8 s) 128 cycles (16 s) 100 128 cycles (16 s) 256 cycles (32 s) 101 256 cycles (32 s) 512 cycles (64 s) 110 512 cycles (64 s) 1024 cycles (128 s) 111 1024 cycles (128 s) 2048 cycles (256 s) care should be taken when choosing the cycle time. a long cycle time means that t min is updated less often. if your system has very fast temperature transients, the dynamic t min control loop will always be lagging. if you choose a cycle time that is too fast, the full benefit of changing t min might not be realized and needs to change again on the next cycle; in effect, it is over- shooting. it is necessary to carry out some calibration to identify the most suitable response time. figure 71 shows the steps taken during the short cycle. is t1(n) ? t1(n ? 1) = 0.5 ? 0.75c is t1(n) ? t1(n ? 1) = 1.0 ? 1.75c is t1(n) ? t1(n ? 1) > 2.0c is t1(n) > (op1 ? hys) yes is t1(n) ? t1(n ? 1) 0.25c do nothing (system is cooling of for constant) yes no no do nothing wait n monitoring cycles previous temperature measurement t1 (n ? 1) current temperature measurement t1(n) operating point temperature op1 decrease t min by 1c decrease t min by 2c decrease t min by 4c 04498-0-077 figure 71. short cycle steps figure 72 shows the steps taken during the long cycle.
adt7467 rev. 0 | page 52 of 80 wait 2n monitoring cycles is t1(n) < low temp limit and t min < high temp limit and t min < op1 and t1(n) > t min is t1(n) > op1 yes increase t min by 1c yes no no decrease t min by 1c current temperature measurement t1(n) operating point temperature op1 do not change 04498-0-078 figure 72. long cycle steps the following examples illustrate some of the circumstances that might cause t min to increase, decrease, or stay the same. example: normal operationno t min adjustment 1. if measured temperature never exceeds the programmed operating point minus the hysteresis temperature, then t min is not adjusted, that is, remains at its current setting. 2. if measured temperature never drops below the low temperature limit, then t min is not adjusted. t min therm limit operating point high temp limit low temp limit actual temp hysteresis 04498-0-079 figure 73. temperature between operating point and low temperature limit because neither the operating point minus the hysteresis temperature nor the low temperature limit has been exceeded, the t min value is not adjusted, and the fan runs at a speed determined by the fixed t min and t range values defined in the automatic fan speed control mode. example: operating point exceededt min reduced when the measured temperature is below the operating point temperature minus the hysteresis, t min remains the same. once the temperature exceeds the operating temperature minus the hysteresis (op ? hyst), t min starts to decrease. this occurs during the short cycle (see figure 71). the rate at which t min decreases depends on the programmed value of n . it also depends on how much the temperature has increased between this monitoring cycle and the last monitoring cycle, that is, if the temperature has increased by 1c, then t min is reduced by 2c. decreasing t min has the effect of increasing the fan speed, thus providing more cooling to the system. if the temperature is slowly increasing only in the range (op ? hyst), that is, 0.25c per short monitoring cycle, then t min does not decrease. this allows small changes in temperature in the desired operating zone without changing t min . the long cycle makes no change to t min in the tempera- ture range (op ? hyst), because the temperature has not exceeded the operating temperature. once the temperature exceeds the operating temperature, the long cycle causes t min to be reduced by 1c every long cycle while the temperature remains above the operating temperature. this takes place in addition to the decrease in t min that would occur due to the short cycle. in figure 74, because the tempera- ture is increasing at a rate 0.25c per short cycle, no reduction in t min takes place during the short cycle. once the temperature has fallen below the operating temperature, t min stays the same. even when the temperature starts to increase slowly, t min stays the same, because the temperature increases at a rate 0.25c per cycle. example: increase t min cycle when the temperature drops below the low temperature limit, t min can increase in the long cycle. increasing t min has the effect of running the fan slower and, therefore, quieter. the long cycle diagram in figure 25 shows the conditions that need to be true for t min to increase. here is a quick summary of those conditions and the reasons they need to be true. t min can increase, if 1. the measured temperature has fallen below the low temperature limit. this means the user must choose the low limit carefully. it should not be so low that the temperature never falls below it, because t min would never increase and the fans would run faster than necessary. 2. t min is below the high temperature limit. t min is never allowed to increase above the high temperature limit. as a result, the high limit should be sensibly chosen, because it determines how high t min can go. 3. t min is below the operating point temperature. t min should never be allowed to increase above the operating point temperature, because the fans would not switch on until the temperature rose above the operating point. 4. the temperature is above t min . the dynamic t min control is turned off below t min .
adt7467 rev. 0| page 53 of 80 t min therm limit o perating point high temp limit low temp limit hysteresis decrease here due to short cycle only t1(n) ? t1 (n ? 1) = 0.5c or 0.75c = > t min decreases by 1c every short cycle decrease here due to long cycle only t1(n) ? t1 (n ? 1) 0.25c and t1(n) > op = > t min decreases by 1c every long cycle no change in t min here due to any cycle, because t1(n) ? t1 (n ? 1) 0.25c and t1(n) < op = > t min stays the same 04498-0-080 actual temp figure 74. effect of exceeding operating point minus hysteresis temperature figure 75 shows how t min increases when the current tempera- ture is above t min and below the low temperature limit, and t min is below the high temperature limit and below the operating point. once the temperature rises above the low temperature limit, t min stays the same. t min operating point high temp limit low temp limit actual temp hysteresis 04498-0-081 therm limit figure 75. increasing t min for quieter operation example: preventing t min from reaching full scale because t min is dynamically adjusted, it is undesirable for t min to reach full scale (127c), because the fan would never switch on. as a result, t min is allowed to vary only within a specified range: 1. the lowest possible value for t min is C127c (twos complement mode) or ?64c (offset 64 mode). 2. t min cannot exceed the high temperature limit. 3. if the temperature is below t min , the fan is switched off or is running at minimum speed and dynamic t min control is disabled. t min prevented from increasing t min o perating point high temp limit low temp limit actual temp hysteresis 04498-0-082 therm limit figure 76. t min adjustments limited by the high temperature limit step 11: monitoring therm using the operating point limit ensures that the dynamic t min control mode is operating in the best possible acoustic position while ensuring that the temperature never exceeds the maxi- mum operating temperature. using the operating point limit allows t min to be independent of system-level issues because of its self-corrective nature. in pc design, the operating point for the chassis is usually the worst-case internal chassis temperature. the optimal operating point for the processor is determined by monitoring the thermal monitor in the intel pentium 4 proces- sor. to do this, the prochot output of the pentium 4 is connected to the therm input of the adt7467. the operating point for the processor can be determined by allowing the current temperature to be copied to the operating point register when the prochot output pulls the therm input low on the adt7467. this gives the maximum temperature at which the pentium 4 can run before clock modulation occurs.
adt7467 rev. 0 | page 54 of 80 enabling the therm trip point as the operating point bits <4:2> of dynamic t min control register 1 (reg. 0x36) enable/disable therm monitoring to program the operating point. dynamic t min control register 1 (0x36) <2> phtr2 = 1, copies the remote 2 current temperature to the remote 2 operating point register, if therm is asserted. the operating point contains the temperature at which therm is asserted. this allows the system to run as quietly as possible without affecting system performance. phtr2 = 0, ignores any therm assertions. the remote 2 operating point register reflects its programmed value. <3> phtl = 1, copies the local current temperature to the local temperature operating point register, if therm is asserted. the operating point contains the temperature at which therm is asserted. this allows the system to run as quietly as possible without affecting system performance. phtl = 0, ignores any therm assertions. the local temperature operating point register reflects its programmed value. <4> phtr1 = 1, copies the remote 1 current temperature to the remote 1 operating point register, if therm is asserted. the operating point contains the temperature at which therm is asserted. this allows the system to run as quietly as possible without affecting system performance. phtr1 = 0, ignores any therm assertions. the remote 1 operating point register reflects its programmed value. enabling dynamic t min control mode bits <7:5> of dynamic t min control register 1 (reg. 0x36) enable/disable dynamic t min control on the temperature channels. dynamic tmin control register 1 (0x36) <5> r2t = 1, enables dynamic t min control on the remote 2 temperature channel. the chosen t min value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. r2t = 0, disables dynamic t min control. the t min value chosen is not adjusted and the channel behaves as described in the automatic fan control overview section. <6> lt = 1, enables dynamic t min control on the local temperature channel. the chosen t min value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. lt = 0, disables dynamic t min control. the t min value chosen is not adjusted and the channel behaves as described in the automatic fan control overview section. <7> r1t = 1, enables dynamic t min control on the remote 1 temperature channel. the chosen t min value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. r1t = 0, disables dynamic t min control. the t min value chosen is not adjusted and the channel behaves as described in the automatic fan control overview section. enhancing system acoustics automatic fan speed control mode reacts instantaneously to changes in temperature, that is, the pwm duty cycle responds immediately to temperature change. any impulses in temperature can cause an impulse in fan noise. for psycho- acoustic reasons, the adt7467 can prevent the pwm output from reacting instantaneously to temperature changes. enhanced acoustic mode controls the maximum change in pwm duty cycle at a given time. the objective is to prevent the fan from cycling up and down, annoying the user. acoustic enhancement mode overview figure 77 gives a top-level overview of the automatic fan control circuitry on the adt7467 and shows where acoustic enhancement fits in. acoustic enhancement is intended as a postdesign tweak made by a system or mechanical engineer evaluating best settings for the system. having determined the optimal settings for the thermal solution, the engineer can adjust the system acoustics. the goal is to implement a system that is acoustically pleasing without causing user annoyance due to fan cycling. it is important to realize that although a system might pass an acoustic noise requirement specification (for example, 36 db), if the fan is annoying, it fails the consumer test.
adt7467 rev. 0| page 55 of 80 04498-0-083 acoustic enhancement rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range tachometer 1 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 2 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator tachometer 3 and 4 measurement pwm config pwm min ramp control (acoustic enhancement) pwm generator 100% figure 77. acoustic enhancement smoothes fan sp eed variations under automatic fan speed control approaches to system acoustic enhancement there are two different approaches to implementing system acoustic enhancement: temperature-centric and fan-centric. the temperature-centric approach involves smoothing transient temperatures as they are measured by a temperature source (for example, remote 1 temperature). the temperature values used to calculate the pwm duty cycle values are smoothed, reducing fan speed variation. however, this approach causes an inherent delay in updating fan speed and causes the thermal characteris- tics of the system to change. it also causes the system fans to stay on longer than necessary, because the fans reaction is merely delayed. the user has no control over noise from different fans driven by the same temperature source. consider, for example, a system in which control of a cpu cooler fan (on pwm1) and a chassis fan (on pwm2) use remote 1 tempera- ture. because the remote 1 temperature is smoothed, both fans are updated at exactly the same rate. if the chassis fan is much louder than the cpu fan, there is no way to improve its acoustics without changing the thermal solution of the cpu cooling fan. the fan-centric approach to system acoustic enhancement controls the pwm duty cycle, driving the fan at a fixed rate (for example, 6%). each time the pwm duty cycle is updated, it is incremented by a fixed 6%. as a result, the fan ramps smoothly to its newly calculated speed. if the temperature starts to drop, the pwm duty cycle immediately decreases by 6% at every update. therefore, the fan ramps smoothly up or down without inherent system delay. consider, for example, controlling the same cpu cooler fan (on pwm1) and chassis fan (on pwm2) using remote 1 temperature. the t min and t range settings have already been defined in automatic fan speed control mode, that is, thermal characterization of the control loop has been optimized. now the chassis fan is noisier than the cpu cooling fan. using the fan-centric approach, pwm2 can be placed into acoustic enhancement mode independently of pwm1. the acoustics of the chassis fan can, therefore, be adjusted without affecting the acoustic behavior of the cpu cooling fan, even though both fans are controlled by remote 1 temperature. the fan-centric approach is how acoustic enhancement works on the adt7467. enabling acoustic enhancem ent for each pwm output enhance acoustics register 1 (reg. 0x62) <3> = 1, enables acoustic enhancement on pwm1 output. enhance acoustics register 2 (reg. 0x63) <7> = 1, enables acoustic enhancement on pwm2 output. <3> = 1, enables acoustic enhancement on pwm3 output. effect of ramp rate on enhanced acoustics mode the pwm signal driving the fan has a period, t , given by the pwm drive frequency, f , because t = 1/ f . for a given pwm period, t , the pwm period is subdivided into 255 equal time slots. one time slot corresponds to the smallest possible increment in the pwm duty cycle. a pwm signal of 33% duty
adt7467 rev. 0 | page 56 of 80 cycle is, therefore, high for 1/3 255 time slots and low for 2/3 255 time slots. therefore, a 33% pwm duty cycle corresponds to a signal that is high for 85 time slots and low for 170 time slots. 170 time slots 85 time slots pwm output (one period) = 255 time slots pwm_out 33% duty cycle 04498-0-084 figure 78. 33% pwm duty cycle represented in time slots the ramp rates in the enhanced acoustics mode are selectable from the values 1, 2, 3, 5, 8, 12, 24, and 48. the ramp rates are discrete time slots. for example, if the ramp rate is 8, then eight time slots are added to the pwm high duty cycle each time the pwm duty cycle needs to be increased. if the pwm duty cycle value needs to be decreased, it is decreased by eight time slots. figure 79 shows how the enhanced acoustics mode algorithm operates. read temperature calculate new pwm duty cycle is new pwm value > previous value? increment previous pwm value by ramp rate yes no decrement previous pwm value by ramp rate 04498-0-085 figure 79. enhanced acoustics algorithm the enhanced acoustics mode algorithm calculates a new pwm duty cycle based on the temperature measured. if the new pwm duty cycle value is greater than the previous pwm value, then the previous pwm duty cycle value is incremented by either 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of the enhance acoustics registers. if the new pwm duty cycle value is less than the previous pwm value, then the previous pwm duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots. each time the pwm duty cycle is incremented or decremented, its value is stored as the previous pwm duty cycle for the next comparison. a ramp rate of 1 corresponds to one time slot, which is 1/255 of the pwm period. in enhanced acoustics mode, incrementing or decrementing by 1 changes the pwm output by 1/255 100%. step 12: ramp rate for acoustic enhancement the optimal ramp rate for acoustic enhancement can be found through system characterization after the thermal optimization has been finished. the effect of each ramp rate should be logged, if possible, to determine the best setting for a given solution. enhanced acoustics re gister 1 (reg. 0x62) <2:0> acou, selects the ramp rate for pwm1. 000 = 1 time slot = 35 s 001 = 2 time slots = 17.6 s 010 = 3 time slots = 11.8 s 011 = 5 time slots = 7 s 100 = 8 time slots = 4.4 s 101 = 12 time slots =3 s 110 = 24 time slots = 1.6 s 111 = 48 time slots = 0.8 s enhance acoustics register 2 (reg. 0x63) <2:0> acou3, selects the ramp rate for pwm3. 000 = 1 time slot = 35 s 001 = 2 time slots = 17.6 s 010 = 3 time slots = 11.8 s 011 = 5 time slots = 7 s 100 = 8 time slots = 4.4 s 101 = 12 time slots = 3 s 110 = 24 time slots = 1.6 s 111 = 48 time slots = 0.8 s <6:4> acou2, selects the ramp rate for pwm2. 000 = 1 time slot = 35 s 001 = 2 time slots = 17.6 s 010 = 3 time slots = 11.8 s 011 = 5 time slots = 7 s 100 = 8 time slots = 4.4 s 101 = 12 time slots = 3 s 110 = 24 time slots = 1.6 s 111 = 48 time slots = 0.8 s another way to view the ramp rates is to measure the time it takes for the pwm output to ramp up from 0% to 100% duty cycle for an instantaneous change in temperature. this can be tested by putting the adt7467 into manual mode and changing the pwm output from 0% to 100% pwm duty cycle. the pwm output takes 35 s to reach 100%, when a ramp rate of 1 time slot is selected.
adt7467 rev. 0| page 57 of 80 figure 80 shows remote temperature plotted against pwm duty cycle for enhanced acoustics mode. the ramp rate is set to 48, which corresponds to the fastest ramp rate. assume that a new temperature reading is available every 115 ms. with these settings, it takes approximately 0.76 s to go from 33% duty cycle to 100% duty cycle (full speed). even though the temperature increases very rapidly, the fan ramps up to full speed gradually. time (s) 140 0 0.76 120 100 80 60 40 20 0 120 100 80 60 40 20 0 r temp (c) pwm cycle (%) 04498-0-086 figure 80. enhanced acoustics mode with ramp rate = 48 figure 81 shows how changing the ramp rate from 48 to 8 affects the control loop. the overall response of the fan is slower. because the ramp rate is reduced, it takes longer for the fan to achieve full running speed. in this case, it takes approximately 4.4 s for the fan to reach full speed. time (s) 120 0 4.4 140 120 100 80 60 40 0 20 100 80 60 40 20 0 r temp (c) pwm duty cycle (%) 04498-0-087 figure 81. enhanced acoustics mode with ramp rate = 8 figure 82 shows the pwm output response for a ramp rate of 2. in this instance, the fan took about 17.6 s to reach full running speed. time (s) 140 0 17.6 120 100 80 60 40 20 0 120 100 80 60 40 20 0 r temp (c) pwm duty cycle (%) 04498-0-088 figure 82. enhanced acoustics mode with ramp rate = 2 figure 83 shows how the control loop reacts to temperature with the slowest ramp rate. the ramp rate is set to 1, while all other control parameters remain the same. with the slowest ramp rate selected, it takes 35 s for the fan to reach full speed. time (s) 0 35 120 100 80 60 40 20 0 140 120 100 80 60 40 20 0 pwm duty cycle (%) r temp (c) 04498-0-089 figure 83. enhanced acoustics mode with ramp rate = 1 as figure 80 to figure 83 show, the rate at which the fan reacts to temperature change is dependent on the ramp rate selected in the enhanced acoustics registers. the higher the ramp rate, the faster the fan reaches the newly calculated fan speed. figure 84 shows the behavior of the pwm output as tempera- ture varies. as the temperature increases, the fan speed ramps up. small drops in temperature do not affect the ramp-up function, because the newly calculated fan speed is still higher than the previous pwm value. enhanced acoustics mode allows the pwm output to be made less sensitive to temperature variations. this is dependent on the ramp rate selected and programmed into the enhanced acoustics registers.
adt7467 rev. 0 | page 58 of 80 9 0 8 0 7 0 6 0 50 4 0 0 3 0 2 0 10 pwm duty cycle (%) r temp (c) 04498-0-090 figure 84. how fan reacts to temperature variation in enhanced acoustics mode slower ramp rates the adt7467 can be programmed for much longer ramp times by slowing the ramp rates. each ramp rate can be slowed by a factor of 4. pwm1 configuration register (reg. 0x5c) <3> slow, 1 slows the ramp rate for pwm1 by 4. pwm2 configuration register (reg. 0x5d) <3> slow, 1 slows the ramp rate for pwm2 by 4. pwm3 configuration register (reg. 0x5e) <3> slow, 1 slows the ramp rate for pwm3 by 4. the following sections list the ramp-up times when the slow bit is set for each pwm output. enhanced acoustics re gister 1 (reg. 0x62) <2:0> acou, selects the ramp rate for pwm1. 000 = 140 s 001 = 70.4 s 010 = 47.2 s 011 = 28 s 100 = 17.6 s 101 = 12 s 110 = 6.4 s 111 = 3.2 s enhance acoustics register 2 (reg. 0x63) <2:0> acou3, selects the ramp rate for pwm3. 000 = 140 s 001 = 70.4 s 010 = 47.2 s 011 = 28 s 100 = 17.6 s 101 = 12 s 110 = 6.4 s 111 = 3.2 s <6:4> acou2, selects the ramp rate for pwm2. 000 = 140 s 001 = 70.4 s 010 = 47.2 s 011 = 28 s 100 = 17.6 s 101 = 12 s 110 = 6.4 s 111 = 3.2 s
adt7467 rev. 0| page 59 of 80 register tables table 16. adt7467 registers address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x21 r vccp reading 9 8 7 6 5 4 3 2 0x00 0x22 r v cc reading 9 8 7 6 5 4 3 2 0x00 0x25 r remote 1 temperature 9 8 7 6 5 4 3 2 0x01 0x26 r local temperature 9 8 7 6 5 4 3 2 0x01 0x27 r remote 2 temperature 9 8 7 6 5 4 3 2 0x01 0x28 r tach1 low byte 7 6 5 4 3 2 1 0 0x00 0x29 r tach1 high byte 15 14 13 12 11 10 9 8 0x00 0x2a r tach2 low byte 7 6 5 4 3 2 1 0 0x00 0x2b r tach2 high byte 15 14 13 12 11 10 9 8 0x00 0x2c r tach3 low byte 7 6 5 4 3 2 1 0 0x00 0x2d r tach3 high byte 15 14 13 12 11 10 9 8 0x00 0x2e r tach4 low byte 7 6 5 4 3 2 1 0 0x00 0x2f r tach4 high byte 15 14 13 12 11 10 9 8 0x00 0x30 r/w pwm1 current duty cycle 7 6 5 4 3 2 1 0 0x00 0x31 r/w pwm2 current duty cycle 7 6 5 4 3 2 1 0 0x00 0x32 r/w pwm3 current duty cycle 7 6 5 4 3 2 1 0 0x00 0x33 r/w remote 1 operating point 7 6 5 4 3 2 1 0 0xa4 yes 0x34 r/w local temp operating point 7 6 5 4 3 2 1 0 0xa4 yes 0x35 r/w remote 2 operating point 7 6 5 4 3 2 1 0 0xa4 yes 0x36 r/w dynamic t min control reg. 1 r2t lt r1t phtr2 phtl phtr1 v ccp lo cyr2 0x00 yes 0x37 r/w dynamic t min control reg. 2 cyr2 cyr2 cyl cyl cyl cyr1 cyr1 cyr1 0x00 yes 0x38 r/w max pwm 1 duty cycle 7 6 5 4 3 2 1 0 0xff 0x39 r/w max pwm 2 duty cycle 7 6 5 4 3 2 1 0 0xff 0x3a r/w max pwm 3 duty cycle 7 6 5 4 3 2 1 0 0xff 0x3d r device id register 7 6 5 4 3 2 1 0 0x68 0x3e r company id number 7 6 5 4 3 2 1 0 0x41 0x3f r revision number ver ver ver ver stp stp stp stp 0x70 0x40 r/w configuration register 1 v cc todis fspdis vxi fspd rdy lock strt 0x01 yes
adt7467 rev. 0 | page 60 of 80 address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x41 r interrupt status register 1 ool r2t lt r1t res v cc v ccp res 0x00 0x42 r interrupt status register 2 d2 d1 f4p fan3 fan2 fan1 ovt res 0x00 0x46 r/w v ccp low limit 7 6 5 4 3 2 1 0 0x00 0x47 r/w v ccp high limit 7 6 5 4 3 2 1 0 0xff 0x48 r/w v cc low limit 7 6 5 4 3 2 1 0 0x00 0x49 r/w v cc high limit 7 6 5 4 3 2 1 0 0xff 0x4e r/w remote 1 temp low limit 7 6 5 4 3 2 1 0 0x01 0x4f r/w remote 1 temp high limit 7 6 5 4 3 2 1 0 0x7f 0x50 r/w local temp low limit 7 6 5 4 3 2 1 0 0x01 0x51 r/w local temp high limit 7 6 5 4 3 2 1 0 0x7f 0x52 r/w remote 2 temp low limit 7 6 5 4 3 2 1 0 0x01 0x53 r/w remote 2 temp high limit 7 6 5 4 3 2 1 0 0x7f 0x54 r/w tach1 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x55 r/w tach1 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x56 r/w tach2 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x57 r/w tach2 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x58 r/w tach3 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x59 r/w tach3 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x5a r/w tach4 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x5b r/w tach4 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x5c r/w pwm1 configuration register bhvr bhvr bhvr inv slow spin spin spin 0x82 yes 0x5d r/w pwm2 configuration register bhvr bhvr bhvr inv slow spin spin spin 0x82 yes 0x5e r/w pwm3 configuration register bhvr bhvr bhvr inv slow spin spin spin 0x82 yes 0x5f r/w remote 1 t range /pwm1 frequency range range range range thrm freq freq freq 0xc4 yes 0x60 r/w local t range /pwm2 frequency range range range range thrm freq freq freq 0xc4 yes
adt7467 rev. 0| page 61 of 80 address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x61 r/w remote 2 t range /pwm3 frequency range range range range thrm freq freq freq 0xc4 yes 0x62 r/w enhance acoustics reg 1 min3 min2 min1 sync en1 acou acou acou 0x00 yes 0x63 r/w enhance acoustics reg 2 en2 acou2 acou2 acou2 en3 acou3 acou3 acou3 0x00 yes 0x64 r/w pwm1 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x65 r/w pwm2 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x66 r/w pwm3 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x67 r/w remote 1 temp t min 7 6 5 4 3 2 1 0 0x9a yes 0x68 r/w local temp t min 7 6 5 4 3 2 1 0 0x9a yes 0x69 r/w remote 2 temp t min 7 6 5 4 3 2 1 0 0x9a yes 0x6a r/w remote 1 therm temp limit 7 6 5 4 3 2 1 0 0xa4 yes 0x6b r/w local therm temp limit 7 6 5 4 3 2 1 0 0xa4 yes 0x6c r/w remote 2 therm temp limit 7 6 5 4 3 2 1 0 0xa4 yes 0x6d r/w remote 1 and local temp/t min hysteresis hysr1 hysr1 hysr1 hysr1 hysl hysl hysl hysl 0x44 yes 0x6e r/w remote 2 temp/t min hysteresis hysr2 hysr2 hysr2 hyrs res res res res 0x40 yes 0x6f r/w xnor tree test enable res res res res res res res xen 0x00 yes 0x70 r/w remote 1 temperature offset 7 6 5 4 3 2 1 0 0x00 yes 0x71 r/w local temperature offset 7 6 5 4 3 2 1 0 0x00 yes 0x72 r/w remote 2 temperature offset 7 6 5 4 3 2 1 0 0x00 yes 0x73 r/w configuration register 2 shdn conv attn avg ain4 ain3 ain2 ain1 0x00 yes 0x74 r/w interrupt mask 1 register ool r2t lt rit res v cc v ccp res 0x00 0x75 r/w interrupt mask 2 register d2 d1 f4p fan3 fan2 fan1 ovt res 0x00 0x76 r/w extended resolution 1 res res v cc v cc v ccp v ccp res res 0x00 0x77 r/w extended resolution 2 tdm2 tdm2 ltmp ltmp tdm1 tdm1 res res 0x00 0x78 r/w configuration register 3 dc4 dc3 dc2 dc1 fast boost therm alert enable 0x00 yes 0x79 r therm timer status register tmr tmr tmr tmr tmr tmr tmr asrt/t mro 0x00 0x7a r/w therm timer limit register limt limt limt limt limt limt limt limt 0x00 0x7b r/w tach pulses per revolution fan4 fan4 fan3 fan3 fan2 fan2 fan1 fan1 0x55
adt7467 rev. 0 | page 62 of 80 address rw description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable? 0x7c r/w configuration register 5 res res res res gpiop gpiod lf/hf twos compl 0x00 yes 0x7d r/w configuration register 4 res res bpatt v ccp res ainl ainl pin 9 func pin 9 func 0x00 yes 0x7e r test register 1 do not write to these registers 0x00 yes 0x7f r test register 2 do not write to these registers 0x00 yes table 17. voltage reading registers (power-on default = 0x00) 1 register address r/w description 0x21 read-only reflects the voltage measurement 2 at the v ccp input on pin 14 (8 msbs of reading). 0x22 read-only reflects the voltage measurement 3 at the v cc input on pin 3 (8 msbs of reading). 1 if the extended resolution bits of these readings are also being read, the extended resolution registers (reg. 0x76, 0x77) must be read first. once the extended resolution registers have been read, the associated msb reading registers are frozen until read. both the extended resolution r egisters and the msb registers are frozen. 2 if v ccp low (bit 1 of the dynamic t min control register 1, 0x36) is set, v ccp can control the sleep state of the adt7467. 3 v cc (pin 3) is the supply voltage for the adt7467. table 18. temperature reading registers (power-on default = 0x01) 1, 2 register address r/w description 0x25 read-only remote 1 temperature reading 3, 4 (8 msb of reading). 0x26 read-only local temperature reading (8 msb of reading). 0x27 read-only remote 2 temperature reading (8 msb of reading). 1 these temperature readings can be in twos complement or offset 64 format; this interpretation is determined by bit 0 of configu ration register 5 (0x7c). 2 if the extended resolution bits of these readings are also being read, the extended resolution registers (reg. 0x76, 0x77) must be read first. once the extended resolution registers have been read, all as sociated msb reading registers get frozen until read. both the extended resolution r egisters and the msb registers are frozen. 3 in twos complement mode, a temperature reading of ?128c (0x80) indicates a diode fault (open or short) on that channel. 4 in offset 64 mode, a temperature reading of ?64c (0x00) indicates a diode fault (open or short) on that channel. table 19. fan tachometer reading registers (power-on default = 0x00) 1 register address r/w description 0x28 read-only tach1 low byte. 0x29 read-only tach1 high byte. 0x2a read-only tach2 low byte. 0x2b read-only tach2 high byte. 0x2c read-only tach3 low byte. 0x2d read-only tach3 high byte. 0x2e read-only tach4 low byte. 0x2f read-only tach4 high byte. 1 these registers count the number of 11.11 s periods (based on an internal 90 khz clock) that occur between a number of consecu tive fan tach pulses (default = 2). the number of tach pulses used to count can be changed using the fan pulses per revolution register (reg. 0x7b). this allows th e fan speed to be accurately measured. because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. both the low and high bytes are then frozen until read. at power-on, these register s contain 0x0000 until such time as the first va lid fan tach measurement is read into these re gisters. this prevents false interrupts from occurring while the fans are spinning up. a count of 0xffff indicates that a fan is one of the following: ? stalled or blocked (object jamming the fan). ? failed (internal ci rcuitry destroyed). ? not populated. (the adt7467 expects to see a fan connected to each tach. if a fan is not connected to that tach, its tach minim um high and low bytes should be set to 0xffff.) ? alternate function, for example, tach4 reconfigured as therm pin. ? 2-wire instead of 3-wire fan. table 20. current pwm duty cycle registers (power-on default = 0x00) 1 register address r/w description 0x30 read/write pwm1 current duty cycl e (0% to 100% duty cycle = 0x00 to 0xff). 0x31 read/write pwm2 current duty cycl e (0% to 100% duty cycle = 0x00 to 0xff). 0x32 read/write pwm3 current duty cycl e (0% to 100% duty cycle = 0x00 to 0xff). 1 these registers reflect the pwm duty cycle driving each fan at any given time. when in automatic fan speed control mode, the ad t7467 reports the pwm duty cycles back through these registers. the pwm duty cycle values vary according to temperature in automatic fan speed control mode. duri ng fan startup, these registers report back 0x00. in software mode, the pwm duty cycle outputs can be set to any duty cycle value by writing to these registers .
adt7467 rev. 0| page 63 of 80 table 21. operating point registers (power-on default = 0x64) 1, 2, 3 register address r/w 3 description 0x33 read/write remote 1 operating point register (default = 100c). 0x34 read/write local temperature opera ting point register (default = 100c). 0x35 read/write remote 2 operating point register (default = 100c). 1 these registers set the target operating point fo r each temperature channel when the dynamic t min control feature is enabled. 2 the fans being controlled are adjusted to mai ntain temperature about an operating point. 3 these registers become read-only when the configuration re gister 1 lock bit is set to 1. an y subsequent attempts to write to th ese registers fail. table 22. register 0x36dynamic t min control register 1 (power-on default = 0x00) 1 bit name r/w description <0> cyr2 read/write msb of 3-bit remote 2 cycle value. the other two bits of the code reside in dynamic t min control register 2 (reg. 0x37). these three bits define the delay time between making subsequent t min adjustments in the control loop, in terms of the number of monitoring cy cles. the system has associat ed thermal time constants that need to be found to optimize the re sponse of fans and the control loop. <1> v ccp lo read/write v ccp lo = 1. when the power is supplied from 3.3 v standby and the core voltage (v ccp ) drops below its v ccp low limit value (reg. 0x46), the following occurs: ? status bit 1 in status register 1 is set. ? smbalert is generated, if enabled. ? prochot monitoring is disabled. ? dynamic t min control is disabled. ? the device is prevented from entering shutdown. ? everything is re-enabled once v ccp increases above the v ccp low limit. <2> phtr1 read/write phtr1 = 1 copies the remote 1 current temperature to the remote 1 operating point register, if therm is asserted. the operating point contai ns the temperature at which therm is asserted, allowing the system to run as quietly as possible without affecting system performance. phtr1 = 0 ignores any therm assertions on the therm pin. the remote 1 operating point register reflects its programmed value. <3> phtl read/write phtl = 1 copies the local channels current temperatur e to the local operating point register, if therm is asserted. the operating point contai ns the temperature at which therm is asserted. this allows the system to run as quietly as possible without affecting system performance. phtl = 0 ignores any therm assertions on the therm pin. the local temperature operating point register reflects its programmed value. <4> phtr2 read/write phtr2 = 1 copies the remote 2 current temperature to the remote 2 operating point register, if therm is asserted. the operating point contai ns the temperature at which therm is asserted, allowing the system to run as quietly as possible without affecting system performance. phtr2 = 0 ignores any therm assertions on the therm pin. the remote 2 operating point register reflects its programmed value. <5> r1t read/write r1t = 1 enables dynamic t min control on the remote 1 temp erature channel. the chosen t min value is dynamically adjusted based on the current temperatur e, operating point, and high and low limits for this zone. r1t = 0 disables dynamic t min control. the t min value chosen is not adjusted, and the channel behaves as described in the fan speed control section. <6> lt read/write lt=1 enables dynamic t min control on the local temperature channel. the chosen t min value is dynamically adjusted based on the current temperature, operat ing point, and high and low limits for this zone. lt = 0 disables dynamic t min control. the t min value chosen is not adjusted, and the channel behaves as described in the fan speed control section. <7> r2t read/write r2t = 1 enables dynamic t min control on the remote 2 temp erature channel. the chosen t min value is dynamically adjusted based on the current temperatur e, operating point, and high and low limits for this zone. r2t = 0 disables dynamic t min control. the t min value chosen is not adjusted and the channel behaves as described in the fan speed control section. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any subsequent attempts to write to thi s register fail.
adt7467 rev. 0 | page 64 of 80 table 23. register 0x37dynamic t min control register 2 (power-on default = 0x00) 1 bit name r/w description <2:0> cyr1 read/write 3-bit remote 1 cycle value. these three bits defi ne the delay time between making subsequent t min adjustments in the control loop for the remote 1 cha nnel, in terms of number of monitoring cycles. the system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. bits decrease cycle increase cycle 000 8 cycles (1 s) 16 cycles (2 s) 001 16 cycles (2 s) 32 cycles (4 s) 010 32 cycles (4 s) 64 cycles (8 s) 011 64 cycles (8 s) 128 cycles (16 s) 100 128 cycles (16 s) 256 cycles (32 s) 101 256 cycles (32 s) 512 cycles (64 s) 110 512 cycles (64 s) 1024 cycles (128 s) 111 1024 cycles (128 s) 2048 cycles (256 s) <5:3> cyl read/write 3-bit local temperature cycle value. these three bits define the delay time between making subsequent t min adjustments in the control loop for the local temper ature channel, in terms of number of monitoring cycles. the system has associated th ermal time constants that need to be found to optimize the response of fans and the control loop. bits decrease cycle increase cycle 000 8 cycles (1 s) 16 cycles (2 s) 001 16 cycles (2 s) 32 cycles (4 s) 010 32 cycles (4 s) 64 cycles (8 s) 011 64 cycles (8 s) 128 cycles (16 s) 100 128 cycles (16 s) 256 cycles (32 s) 101 256 cycles (32 s) 512 cycles (64 s) 110 512 cycles (64 s) 1024 cycles (128 s) 111 1024 cycles (128 s) 2048 cycles (256 s) <7:6> cyr2 read/write 2 lsbs of 3-bit remote 2 cycle value. the msb of the 3-bit code resides in dynamic t min control register 1 (reg. 0x36). these three bits define the delay time between making subsequent t min adjustments in the control loop for the remote 2 channel, in terms of numb er of monitoring cycles. the system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. bits decrease cycle increase cycle 000 8 cycles (1 s) 16 cycles (2 s) 001 16 cycles (2 s) 32 cycles (4 s) 010 32 cycles (4 s) 64 cycles (8 s) 011 64 cycles (8 s) 128 cycles (16 s) 100 128 cycles (16 s) 256 cycles (32 s) 101 256 cycles (32 s s) 512 cycles (64 s) 110 512 cycles (64 s) 1024 cycles (128 s) 111 1024 cycles (128 s) 2048 cycles (256 s) 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any subsequent attempts to write to thi s register fail. table 24. maximim pwm duty cycle (power-on default = 0xff) 1, 2 register address r/w 2 description 0x38 read/write maximum duty cycle for pwm1 output, default = 100% (0xff). 0x39 read/write maximum duty cycle for pwm2 output, default = 100% (0xff). 0x3a read/write maximum duty cycle for pwm3 output, default = 100% (0xff). 1 these registers set the maximum pwm duty cycle of the pwm output . 2 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail.
adt7467 rev. 0| page 65 of 80 table 25. register 0x40configuration register 1 (power-on default = 0x01) bit name r/w description <0> strt read/write logic 1 enables monitoring and pwm control outputs based on the limit settings programmed. logic 0 disables monitoring and pwm control ba sed on the default power-up limit settings. note that the limit values programmed are preserved even if a logic 0 is written to this bit and the default settings are enabled. this bit becomes read-only and cannot be changed once bit 1 (lock bit) has been written. all limit registers should be programmed by bios before setting this bit to 1. (lockable.) <1> lock write once logic 1 locks all limit values to their current settings. on ce this bit is set, all lockable registers become read- only and cannot be modified until the adt7467 is pow ered down and powered up again. this prevents rogue programs such as viruses from modifying critical system limit settings. (lockable.) <2> rdy read-only this bit is set to 1 by the adt7467 to indicate only that the device is fully powered up and ready to begin system monitoring. <3> fspd read/write when set to 1, this bit runs all fans at full speed. po wer-on default = 0. this bit does not get locked at any time. <4> vxi read/write bios should set this bit to a 1 when the adt7467 is configured to measure current from an adi adopt? vrm controller and to measure the cpus core voltage. this bit allows monitoring software to display cpu watts usage. (lockable.) <5> fspdis read/write logic 1 disables fan spin-up for two tach pulses. instea d, the pwm outputs go high for the entire fan spin- up timeout selected. <6> todis read/write when this bit is set to 1, the sm bus timeout feature is enabled. this allows the adt7467 to be used with smbus controllers that cannot handle smbus timeouts. (lockable.) <7> v cc read/write when this bit is set to 1, the adt7467 rescales its v cc pin to measure 5 v supply. if this bit is 0, the adt7467 measures v cc as a 3.3 v supply. (lockable.) table 26. register 0x41interrupt status register 1 (power-on default = 0x00) bit name r/w description <1> v ccp read-only v ccp = 1 indicates that the v ccp high or low limit has been exceeded. this bit is cleared on a read of the status register only if the erro r condition has subsided. <2> v cc read-only v cc = 1 indicates that the v cc high or low limit has been exceeded. this bit is cleared on a read of the status register only if the erro r condition has subsided. <4> r1t read-only r1t = 1 indicates that the remote 1 low or high tempera ture has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. <5> lt read-only lt = 1 indicates that the local low or high temperature ha s been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. <6> r2t read-only r2t = 1 indicates that the remote 2 low or high tempera ture has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. <7> ool read-only ool = 1 indicates that an out-of-limit even t has been latched in status register 2. this bit is a logical or of all status bits in status register 2. soft ware can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by sta tus register 2 are out-of-limit , which saves the need to read status register 2 every interrupt or polling cycle.
adt7467 rev. 0 | page 66 of 80 table 27. register 0x42interrupt status register 2 (power-on default = 0x00) bit name r/w description <1> ovt read-only ovt = 1 indicates that one of the therm overtemperature limits has been exceeded. this bit is cleared on a read of the status register when the temperature drops below therm Ct hyst . <2> fan1 read-only fan1 = 1 indicates that fan 1 has dropped below minimum speed or has stalled. this bit is not set when the pwm1 output is off. <3> fan2 read-only fan2 = 1 indicates that fan 2 has dropped below minimum speed or has stalled. this bit is not set when the pwm2 output is off. <4> fan3 read-only fan3 = 1 indicates that fan 3 has dropped below minimum speed or has stalled. this bit is not set when the pwm3 output is off. <5> f4p read-only f4p = 1 indicates that fan 4 has dropped below minimum speed or has stalled. this bit is not set when the pwm3 output is off. read/write when pin 9 is programmed as a gpio output, writing to this bit determines the logic output of the gpio. read-only if pin 9 is configured as the therm timer input for therm monitoring, then this bi t is set when the therm assertion time exceeds the l imit programmed in the therm limit register (reg. 0x7a). <6> d1 read-only d1 = 1 indicates either an ope n or short circuit on the thermal diode 1 inputs. <7> d2 read-only d2 = 1 indicates either an ope n or short circuit on the thermal diode 2 inputs. table 28. voltage limit registers 1 register address r/w description 2 power-on default 0x46 read/write v ccp low limit. 0x00 0x47 read/write v ccp high limit. 0xff 0x48 read/write v cc low limit. 0x00 0x49 read/write v cc high limit. 0xff 1 setting the configuration register 1 lock bit has no effect on these registers. 2 high limits: an interrupt is gene rated when a value exceeds its hi gh limit (> comparison). low limits: an interrupt is generate d when a value is equal to or below its low limit ( comparison). table 29. temperature limit registers 1 register address r/w description 2 power-on default 0x4e read/write remote 1 temperature low limit. 0x81 0x4f read/write remote 1 te mperature high limit. 0x7f 0x50 read/write local temperature low limit. 0x81 0x51 read/write local temperature high limit. 0x7f 0x52 read/write remote 2 te mperature low limit. 0x81 0x53 read/write remote 2 temp erature high limit. 0x7f 1 exceeding any of these temperature limits by 1c causes the approp riate status bit to be set in the interrupt status register. setting the configuration register 1 lock bit has no effect on these registers. 2 high limits: an interrupt is gene rated when a value exceeds its hi gh limit (> comparison). low limits: an interrupt is generate d when a value is equal to or below its low limit ( comparison). table 30. fan tachometer limit registers 1 register address r/w description power-on default 0x54 read/write tach1 minimum low byte. 0xff 0x55 read/write tach1 minimum high byte/single channel adc channel select. 0xff 0x56 read/write tach2 minimum low byte. 0xff 0x57 read/write tach2 minimum high byte. 0xff 0x58 read/write tach3 minimum low byte. 0xff 0x59 read/write tach3 minimum high byte. 0xff 0x5a read/write tach4 minimum low byte. 0xff 0x5b read/write tach4 minimum high byte. 0xff 1 exceeding any of the tach limit registers by 1 indicates that the fan is running too slowly or has stalled. the appropriate sta tus bit is set in inte rrupt status register 2 to indicate the fan failure. setting the configuration register 1 lock bit has no effect on these registers.
adt7467 rev. 0| page 67 of 80 table 31. register 0x55tach 1 minimum high byte (power-on default = 0xff) bit name r/w description <4:0> reserved read-only these bits are reserved when bit 6 of config 2 register (0x73) is set (single-channel adc mode). otherwise, these bits represent bits <4:0> of the tach1 minimum high byte. <7:5> scadc read/write when bit 6 of config 2 register (0x73) is set (single-channel adc mode), these bits are used to select the only channel from wh ich the adc makes measurements. otherwise, these bits represent bits <7:5> of the tach1 minimum high byte. table 32. pwm configuration registers register address r/w 1 description power-on default 0x5c read/write pwm1 configuration. 0x82 0x5d read/write pwm2 configuration. 0x82 0x5e read/write pwm3 configuration. 0x82 bit name r/w description <2:0> spin read/write these bits control the startup timeout for pwmx. the pwm output stays high until two valid tach rising edges are seen from the fan. if there is not a valid tach signal during the fan tach measurement directly after the fan startup timeout period, then the tach measurement reads 0xffff and status register 2 reflects the fan fault. if the tach minimum high and low bytes contain 0xffff or 0x 0000, then the status register 2 bit is not set, even if the fan has not started. 000 = no startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 s 110 = 2 s 111 = 4 s <3> slow read/write slow = 1 makes the ramp rates for acoustic enhancement four times longer. <4> inv read/write this bit inverts the pwm outp ut. the default is 0, which corresponds to a logic high output for 100% duty cycle. setting this bit to 1 inverts the pwm output, so 100% duty cycle corresponds to a logic low output. <7:5> bhvr read/write these bits assign each fan to a particular temperature sens or for localized cooling. 000 = remote 1 temperature contro ls pwmx (automatic fan control mode). 001 = local temperature controls pwmx (automatic fan control mode). 010 = remote 2 temperature contro ls pwmx (automatic fan control mode). 011 = pwmx runs full speed. 100 = pwmx disabled (default). 101 = fastest speed calculated by loca l and remote 2 temperature controls pwmx. 110 = fastest speed calculated by a ll three temperature channel controls pwmx. 111 = manual mode. pwm duty cycle register s (reg. 0x30 to reg. 0x32) become writable. 1 these registers become read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th ese registers fail.
adt7467 rev. 0 | page 68 of 80 table 33. temp t range /pwm frequency registers register address r/w 1 description power-on default 0x5f read/write remote 1 t range /pwm1 frequency. 0xc4 0x60 read/write local temperature t range /pwm2 frequency. 0xc4 0x61 read/write remote 2 t range /pwm3 frequency. 0xc4 bit name r/w description <2:0> freq read/write these bi ts control the pwmx frequency. 000 = 11.0 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz (default) 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz <3> thrm read/write thrm = 1 causes the therm pin (pin 9) to assert lo w as an output when this temperature channels therm limit has been exceeded by 0.25c. the therm pin remains asserted until the temperature is equal to or below the therm limit. the minimum time that therm asserts is one monitoring cycle. this allows clock modulation of devices that incorporate this feature. thrm = 0 makes the therm pin act as an input only, for example, for pentium 4 prochot monitoring, when pin 9 is configured as therm . <7:4> range read/write these bits determine the pwm duty cycle vs . the temperature slope for automatic fan control. 0000 = 2c 0001 = 2.5c 0010 = 3.33c 0011 = 4c 0100 = 5c 0101 = 6.67c 0110 = 8c 0111 = 10c 1000 = 13.33c 1001 = 16c 1010 = 20c 1011 = 26.67c 1100 = 32c (default) 1101 = 40c 1110 = 53.33c 1111 = 80c 1 these registers become read-only when the configuration re gister 1 lock bit is set. any fur ther attempts to wr ite to these regi sters have no effect.
adt7467 rev. 0| page 69 of 80 table 34. register 0x62enhanced acoustic s register 1 (power-on default = 0x00) bit name r/w 1 description <2:0> acou read/write these bits select the ramp rate a pplied to the pwm1 output. instead of pwm1 jumping instantaneously to its newly calculated speed, pwm1 ramps gracefully at the rate determined by these bits. this feature enhances the acoustics of the fan being driven by the pwm1 output. time slot increase time for 33% to 100% 000 = 1 35 s 001 = 2 17.6 s 010 = 3 11.8 s 011 = 4 7 s 100 = 8 4.4 s 101 = 12 3 s 110 = 24 1.6 s 111 = 48 0.8 s <3> en1 read/write when this bit is 1, ac oustic enhancement is en abled on pwm1 output. <4> sync read/write sync = 1 synchronizes fan speed measurements on ta ch2, tach3, and tach4 to pwm3. this allows up to three fans to be driven from pwm3 o utput and their speeds to be measured. sync = 0 synchronizes only tach3 and tach4 to pwm3 output. <5> min1 read/write when the adt7467 is in automatic fan control mode, this bit defines whethe r pwm1 is off (0% duty cycle) or at pwm1 minimum duty cycle when the co ntrolling temperature is below its t min C hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm1 minimum duty cycle below t min C hysteresis. <6> min2 read/write when the adt7467 is in automatic fan speed control mo de, this bit defines whethe r pwm2 is off (0% duty cycle) or at pwm2 minimum duty cycle when the controlling temperature is below its t min C hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm 2 minimum duty cycle below t min C hysteresis. <7> min3 read/write when the adt7467 is in automatic fan speed control mo de, this bit defines whethe r pwm3 is off (0% duty cycle) or at pwm3 minimum duty cycle when the controlling temperature is below its t min C hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm3 minimum duty cycle below t min C hysteresis. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect.
adt7467 rev. 0 | page 70 of 80 table 35. register 0x63enhanced acoustic s register 2 (power-on default = 0x00) bit name r/w 1 description <2:0> acou3 read/write these bits select the ramp rate a pplied to the pwm3 output. instead of pwm3 jumping instantaneously to its newly calculated speed, pwm3 ramps gracefully at the rate determined by these bits. this effect enhances the acoustics of the fan being driven by the pwm3 output. time slot increase time for 33% to 100% 000 = 1 35 s 001 = 2 17.6 s 010 = 3 11.8 s 011 = 5 7 s 100 = 8 4.4 s 101 = 12 3 s 110 = 24 1.6 s 111 = 48 0.8 s < 3 > en3 read/write when this bit is 1, ac oustic enhancement is en abled on pwm3 output. <6:4> acou2 read/write these bits select the ramp rate a pplied to the pwm2 output. instead of pwm2 jumping instantaneously to its newly calculated speed, pwm2 ramps gracefully at the rate determined by these bits. this effect enhances the acoustics of the fans being driven by the pwm2 output. time slot increase time for 33% to 100% 000 = 1 35 s 001 = 2 17.6 s 010 = 3 11.8 s 011 = 5 7 s 100 = 8 4.4 s 101 = 12 3 s 110 = 24 1.6 s <7> en2 read/write when this bit is 1, ac oustic enhancement is en abled on pwm2 output. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect. table 36. pwm minimum duty cycle registers register address r/w 1 description power-on default 0x64 read/write pwm1 minimum duty cycle. 0x80 (50% duty cycle) 0x65 read/write pwm2 minimum duty cycle. 0x80 (50% duty cycle) 0x66 read/write pwm3 minimum duty cycle. 0x80 (50% duty cycle) bit name r/w 1 description <7:0> pwm duty cycle read/write these bits define the pwm min duty cycle for pwmx. 0x00 = 0% duty cycle (fan off). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xff = 100% duty cycle (fan full speed). 1 these registers become read -only when the adt7467 is in automatic fan control mode. table 37. t min registers 1 register address r/w 2 description power-on default 0x67 read/write remote 1 temperature t min . 0x5a (90c) 0x68 read/write local temperatue t min . 0x5a (90c) 0x69 read/write remote 2 temperature t min . 0x5a (90c) 1 these are the t min registers for each temperature channel. when the temperature measured exceeds t min , the appropriate fan runs at minimum speed and increases with temperature according to t range . 2 these registers become read-only when the configuration re gister 1 lock bit is set. any fur ther attempts to wr ite to these regi sters have no effect.
adt7467 rev. 0| page 71 of 80 table 38. therm limit registers 1 register address r/w 2 description power-on default 0x6a read/write remote 1 therm limit. 0x64 (100c) 0x6b read/write local therm limit. 0x64 (100c) 0x6c read/write remote 2 therm limit. 0x64 (100c) 1 if any temperature me asured exceeds its therm limit, all pwm outputs drive their fans at 100% duty cycle. this is a fail-safe mechanism incorporated to cool the system in the event of a critical overtemperature. it also ensures some level of cooling in the event that software or hardware locks up. if set to 0x80, this feature is disabled. the pwm output remains at 100% until the temperature drops below therm limit C hysteresis. if the therm pin is programmed as an output, then exceeding these limits by 0.25c can cause the therm pin to assert low as an output. 2 these registers become read-only when the configuration re gister 1 lock bit is set to 1. an y further attempts to write to these registers have no effect. table 39. temperature/t min hysteresis registers 1 register address r/w 2 description power-on default 0x6d read/write remote 1 and local temperature hysteresis. 0x44 <3:0> hysl local temperature hyseresis. 0c to 15c of hysteresis can be applied to the local temperature afc and dynamic t min control loops. <7:4> hysr1 remote 1 temperature hyseresis. 0c to 15c of hysteresis can be applied to the remote 1 temperature afc and dynamic t min control loops. 0x6e read/write remote 2 temperature hysteresis. 0x40 <7:4> hysr2 local temperature hyseresis. 0c to 15c of hysteresis can be applied to the local temperature afc and dynamic t min control loops. 1 each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. once the temperatur e for that channel falls below its t min value, the fan remains running at pwm min duty cycle until the temperature = t min C hysteresis. up to 15c of hysteresis can be assigned to any temperature channel. the hysteresis value chosen also applies to that temperature channel, if its therm limit is exceeded. the pwm output being controlled goes to 100%, if the therm limit is exceeded and remains at 100 % until the temperature drops below therm C hysteresis. for acoustic reasons, it is recommended that the hysteresis value not be programmed less than 4c. setting the hyster esis value lower than 4c causes the fan to switch on and off regularly when the te mperature is close to t min . 2 these registers become read-only when the configuration re gister 1 lock bit is set to 1. an y further attempts to write to these registers have no effect. table 40. xnor tree test enable register address r/w 1 description power-on default 0x6f read/write xnor tree test enable register. 0x00 <0> xen if the xen bit is set to 1, the device enters the xnor tree test mode. clearing the bit removes the device from the xnor tree test mode. <7:1> reserved unused. do not write to these bits. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect. table 41. remote 1 temperature offset register address r/w 1 description power-on default 0x70 read/write remote 1 temperature offset. 0x00 <7:0> read/write allows a twos complement offset value to be automatically added to or subtracted from the remote 1 temperature re ading. this is to compensate for any inherent system offsets such as pcb trace resistance. lsb value = 0.5c. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect.
adt7467 rev. 0 | page 72 of 80 table 42. local temperature offset register address r/w 1 description power-on default 0x71 read/write local temperature offset. 0x00 <7:0> read/write allows a twos complement offset value to be automatically added to or subtracted from the local temperature reading. lsb value = 0.5c. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect. table 43. remote 2 temperature offset register address r/w 1 description power-on default 0x72 read/write remote 2 temperature offset. 0x00 <7:0> read/write allows a twos complement offset value to be automatically added to or subtracted from the remote 2 temperature re ading. this is to compensate for any inherent system offsets such as pcb trace resistance. lsb value = 0.5c. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect. table 44. register 0x73configuration register 2 (power-on default = 0x00) bit name r/w 1 description 0 ain1 read/write ain1 = 0, speed of 3-wire fans measured using the tach output from the fan. ain1 = 1, pin 6 is reconfigured to meas ure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. ain voltage threshold is set via configuration register 4 (reg. 0x7d). only relevant in low frequency mode. 1 ain2 read/write ain2 = 0, speed of 3-wire fans measured using the tach output from the fan. ain2 = 1, pin 7 is reconfigured to meas ure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. ain voltage threshold is set via configuration register 4 (reg. 0x7d). only relevant in low frequency mode. 2 ain3 read/write ain3 = 0, speed of 3-wire fans measured using the tach output from the fan. ain3 = 1, pin 4 is reconfigured to meas ure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. ain voltage threshold is set via configuration register 4 (reg. 0x7d). only relevant in low frequency mode. 3 ain4 read/write ain4 = 0, speed of 3-wire fans measured using the tach output from the fan. ain4 = 1, pin 9 is reconfigured to meas ure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. ain voltage threshold is set via configuration register 4 (reg. 0x7d). only relevant in low frequency mode. 4 avg read/write avg = 1, averaging on the temperature an d voltage measurements is turned off. this allows measurements on each ch annel to be made much faster. 5 attn read/write attn = 1, the adt7467 removes the attenuators from the v ccp input. the v ccp input can be used for other functions such as connecting up external sensors. 6 conv read/write conv = 1, the adt7467 is put into a single -channel adc conversion mode. in this mode, the adt7467 can be made to read continuously from one input only, for example, remote 1 temperature. the appropriate adc channel is selected by writing to bits <7:5> of tach1 min imum high byte register (0x55). bits <7:5> reg. 0x55 000 reserved 001 v ccp 010 v cc (3.3 v) 011 reserved 100 reserved 101 remote 1 temperature 110 local temperature 111 remote 2 temperature 7 shdn read/write shdn = 1, adt7467 goes into shutdown mode. all pwm outputs assert low (or high depending on state of inv bit) to switch off all fans. the pwm current duty cycle registers read 0x00 to indicate that the fans are not being driven. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect.
adt7467 rev. 0| page 73 of 80 table 45. register 0x74interrupt mask register 1 (power-on default <7:0> = 0x00) bit name r/w description 1 v ccp read/write v ccp = 1, masks smbalert for out-of-limit conditions on the v ccp channel. 2 v cc read/write v cc = 1, masks smbalert for out-of-limit conditions on the v cc channel. 4 r1t read/write r1t = 1, masks smbalert for out-of-limit conditions on th e remote 1 temperature channel. 5 lt read/write lt = 1, masks smbalert for out-of-limit conditions on the local temperature channel. 6 r2t read/write r2t = 1, masks smbalert for out-of-limit conditions on th e remote 2 temperature channel. 7 ool read/write ool = 1, masks smbalert for any out-of-limit condition in status register 2. table 46. register 0x75interrupt mask register 2 (power-on default <7:0> = 0x00) bit name r/w description 1 ovt read only ovt = 1, masks smbalert for overtemperature therm conditions. 2 fan1 read/write fan1 = 1, masks smbalert for a fan 1 fault. 3 fan2 read/write fan2 = 1, masks smbalert for a fan 2 fault. 4 fan3 read/write fan3 = 1, masks smbalert for a fan 3 fault. 5. f4p read/write f4p = 1, masks smbalert for a fan 4 fault. if the tach4 pin is being used as the therm input, this bit masks smbalert for a therm timer event. 6 d1 read/write d1 = 1, masks smbalert for a diode open or short on a remote 1 channel. 7 d2 read/write d2 = 1, masks smbalert for a diode open or short on a remote 2 channel. table 47. register 0x76extended resolution register 1 1 bit name r/w description <3:2> v ccp read-only v ccp lsbs. holds the 2 lsbs of the 10-bit v ccp measurement. <5:4> v cc read-only v cc lsbs. holds the 2 lsbs of the 10-bit v cc measurement. 1 if this register is read, this register and the registers holding the msb of each reading are frozen until read. table 48. register 0x77extended resolution register 2 1 bit name r/w description <3:2> tdm1 read-only remote 1 temperature lsbs. holds th e 2 lsbs of the 10-bit remote 1 temperature measurement. <5:4> ltmp read-only local temperature lsbs. holds th e 2 lsbs of the 10-bit local temperature measurement. <7:6> tdm2 read-only remote 2 temperature lsbs. holds the 2 lsbs of the 10-bit remote 2 temperature measurement. 1 if this register is read, this register and the registers holding the msb of each reading are frozen until read.
adt7467 rev. 0 | page 74 of 80 table 49. register 0x78configuration register 3 (power-on default = 0x00) bit name r/w 1 description <0> alert read/write alert = 1, pin 5 (pwm2/ smbalert ) is configured as an smbalert interrupt output to indicate out- of-limit error conditions. <1> therm read/write therm enable = 1 enables therm timer monitoring functionality on pin 9. also determined by bits 0 and 1 (pin9func) of configuration register 4. when therm is asserted, if the fans are running and the boost bit is set, the fans run at full speed. alternatively, therm can be programmed so that a timer is triggered to time how long therm has been asserted. <2> boost read/write when therm is an input and boost = 1, assertion of therm causes all fans to run at the maximum programmed duty cycle for fail-safe cooling. <3> fast read/write fast = 1, enables fast tach measurements on a ll channels. this increases the tach measurement rate from once per second to once every 250 ms (4 ). <4> dc1 read/write dc1 = 1, enables tach measurements to be continuo usly made on tach1. fans must be driven by dc. setting this bit prevents pulse stretching, beca use it is not required for dc-driven motors. <5> dc2 read/write dc2 = ,1 enables tach measurements to be continuo usly made on tach2. fans must be driven by dc. setting this bit prevents pulse stretching, be cause it is not required for dc-driven motors. <6> dc3 read/write dc3 = 1, enables tach measurements to be continuo usly made on tach3. fans must be driven by dc. setting this bit prevents pulse stretching, be cause it is not required for dc-driven motors. <7> dc4 read/write dc4 = 1, enables tach measurements to be continuo usly made on tach4. fans must be driven by dc. setting this bit prevents pulse stretching, be cause it is not required for dc-driven motors. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect. table 50. register 0x79 therm timer status register (power-on default = 0x00) bit name r/w description <7:1> tmr read-only times how long therm input is asserted. these seven bits read zero until the therm assertion time exceeds 45.52 ms. <0> asrt/ tmr0 read-only this bit is set high on the assertion of the therm input, and is cleared on read. if the therm assertion time exceeds 45.52 ms, this bit is set an d becomes the lsb of the 8-bit tmr reading. this allows therm assertion times from 45.52 ms to 5.82 s to be reported back with a resolution of 22.76 ms. table 51. register 0x7a therm timer limit register (power-on default = 0x00) bit name r/w description <7:0> limt read/write sets maximum therm assertion length allowed before an inte rrupt is generated. this is an 8-bit limit with a resolution of 22.76 ms allowing therm assertion limits of 45.52 ms to 5.82 s to be programmed. if the therm assertion time exceeds this limit, bit 5 (f4p) of interrupt status register 2 (reg. 0x42) is set. if the limit value is 0x00, then an interrupt is ge nerated immediately on the assertion of the therm input.
adt7467 rev. 0| page 75 of 80 table 52. register 0x7btach pulses per revo lution register (power-on default = 0x55) bit name r/w description <1:0> fan1 read/write sets number of pulses to be co unted when measuring fan 1 speed. can be used to determine fan pulses per revolution for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <3:2> fan2 read/write sets number of pulses to be co unted when measuring fan 2 speed. can be used to determine fan pulses per revolution for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <5:4> fan3 read/write sets number of pulses to be co unted when measuring fan 3 speed. can be used to determine fan pulses per revolution for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <7:6> fan4 read/write sets number of pulses to be co unted when measuring fan 4 speed. can be used to determine fan pulses per revolution for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 table 53. register 0x7cconfiguration register 5 (power-on default = 0x00) bit name r/w 1 description <0> 2sc read/write 2sc = 1, sets the tempera ture range to twos complement temperature range. 2sc = 0, changes the temperature range to offs et 64. when this bit is changed, the adt7467 interprets all relevant temperature regi ster values as defined by this bit. <1> hf/lf sets the pwm drive frequency to high frequency mode (0) or low frequency mode (1). <2> gpiod gpio direction. when gpio function is enabled, this determines whethe r the gpio is an input (0) or an output (1). <3> gpiop gpio polarity. when the gpio function is enab led and is programmed as an output, this bit determines whether the gpio is active low (0) or high (1). <4:7> res unused. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect.
adt7467 rev. 0 | page 76 of 80 table 54. register 0x7dconfiguration register 4 (power-on default = 0x00) bit name r/w 1 description <1:0> pin9func read/write these bits set the functionality of pin 9: 00 = tach4 (default) 01 = bidirectional therm 10 = smbalert 11 = gpio <3:2> ainl read/write these two bits define the input threshold for 2-wire fan speed me asurements (low frequency mode only): 00 = 20 mv 01 = 40 mv 10 = 80 mv 11 = 130 mv <4:7> res unused. <5> bpattv ccp bypass v ccp attenuator. when set, the measurement scale for this channel changes from 0 v (0x00) to 2.2965v (0xff) . <6:7> res unused. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any further attempts to write to this r egister have no effect. table 55. register 0x7emanufacturers te st register 1 (power-on default = 0x00) bit name r/w description <7:0> reserved read-only manufacturers test register. these bits are reser ved for manufacturers test purposes and should not be written to under normal operation. table 56. register 0x7fmanufacturers te st register 2 (power-on default = 0x00) bit name r/w description <7:0> reserved read-only manufacturers test register. these bits are reser ved for manufacturers test purposes and should not be written to under normal operation.
adt7467 rev. 0| page 77 of 80 adt7467 programming block diagram temperature measured is out of limits diode fault. for remote chann els only fan fault configuration 2 (0x73) drive pwm outputs high/low v cc low limit (0x48) v cc high limit (0x49) t hyst t hyst min pwm 0% duty cycle t min t therm pwm duty cycle/relative fan speed t range = slope heating cooling automatic fan control temperature 100% duty cycle max pwm automatic fan control therm is input/output pwm 2 smbalert v ccp measurement (0x47) 8 cycles (1s) 16 cycles (2s) 32 cycles (4s) 64 cycles (8s) 128 cycles (16s) 256 cycles (32s) 512 cycles (64s) 1024 cycles (128s) temp t range ,pwm freq,therm enable (0x5f, 0x60, 0x61) interrupts on status register 2 therm timer limit has been exceeded software interrupts hardware interrupts rescale v cc (5v/3.3v) start monitoring lock settings run fans at fullspeed ready configuration 1 (0x40) average temp and voltage measurements measure from 2- or 3- wire fans single channel adc mode rescale v ccp input (5v/3.3v) v cc remote temp1 remote temp2 local temp measurement msbs (0x25-0x27) measurement lsbs (0x77) if these registers are used, all temperature measurement msb registers are frozen until all temperature measurement msb registers are read. temperature measurement high limit low limit (0x4e-0x53) temperature measurement (0x25, 0x26,0x27) temperature offset (0x70-0x72) gpio polarity temperature range gpio direction fan drive high/low frequency mode configuration 5 (0x7c) twos complement offset 64 increase cycle time change cycle time decrease cycle time 16 cycles (2s) 32 cycles (4s) 64 cycles (8s) 128 cycles (16s) 256 cycles (32s) 512 cycles (64s) 1024 cycles (128s) 2048 cycles (256s) therm as (timer) input therm timer limit (0x7a) therm temp limits (0x6a, 0x6b, 0x6c) therm timer status (0x79) v ccp low limit (0x46) v ccp high limit (0x47) dynamic t min control (0x36, 0x37) v ccp low (sleep) phtxx current temperature of selected channel is copied to r elevant operating point register on assertion of therm enable dynamic t min control on individual channel cyxx t min adjustment cycle time selected pwm ramp-up speed 35s (33%-100%) 17.6s (33%-100%) 18s (33%-100%) 7s (33%-100%) 4.4s (33%-100%) 3s (33%-100%) 1.6s (33%-100%) 0.8s (33%-100%) enhance acoustics (0x62,0x63) allow selected pwm to turn off when temp is below t min ?hyst enable selected pwm ramp-up speed sync fan speed measurements v cc measurement (0x22) fast tach measurements enable therm therm boost (fan must be running) configuration 3 (0x78) enable continuous fan speed measurement (only used when fans are powered by dc and not pwm) remote 1 temp controls selected pwm drive (afc mode) local temp controls selected pwm drive (afc mode) remote 2 temp controls selected pwm drive (afc mode) selected pwm drive runs full speed selected pwm drive disabled (default) fastest speed calculated by local and remote 2 temp controls selected pwm drive fastest speed calculated by all 3 temperature channel controls manual mode. pwm duty cycle registers (0x30-0x32) become writable fan behavior fan spinup timeout no timeout 100ms 250ms (default) 400ms 667ms 1s 2s 4s pwm configuration (0x5c-0x5e) 1 pulse per rev fan tach pulses per rev (0x7b) 2 pulse per rev 3 pulse per rev 4 pulse per rev fan 16-bit measurement (0x28-0x2f) low byte must be read first. when the low byte is read, registers are locked until the associated high byte is read. pwm min duty cycle (automatic mode only) (0x64-0x66) fantach 16-bit minimum limit (0x54-0x5b) pwm duty cycle (manual mode only) (0x30-0x32) 8c 10c 13.33c 16c 20c 26.67c 32c 40c 53.33c 80c 2.5c 2c 3.33c 4c 5c 6.67c pwm frequency 20mv input threshold for 2-wire fans (ainl) 40mv 80mv 130mv bypass v ccp attenuator therm smbalert gpio mask interrupt? (0x74,0x75) interrupt status (0x41, 0x42) smbalert shutdown tach 4 set pin 14/20 functionality configuration 4 (0x7d) interrupt general voltages fans temperature therm xnor test (0x6f) operating point (0x33-0x35) therm as overtemp output therm f4p average temp and voltage measurements (see configuration 2, 0x73) slow improved acoustic ramp-up max fan speed (max pwm duty cycle) (0x38-0x3a) invert pwm output v ccp t min . min temp that causes selected fans to run (0x67-0x69) temperature hysteresis (thyst) (0x6d, 0x6e) configure pin 10 t range 11.0hz 14.7hz 22.1hz 29.4hz 35.3hz 44.1hz 58.8hz 88.2hz adt7467/adt7468 programming block diagram 04498-0-044 figure 85.
adt7467 rev. 0 | page 78 of 80 outline dimensions 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.154 bsc 0.236 bsc compliant to jedec standards mo-137ab 0.193 bsc figure 86. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches ordering guide model temperature range package description package option ADT7467ARQ C40c to +120c 16-lead qsop rq-16 ADT7467ARQ-reel C40c to +120c 16-lead qsop rq-16 ADT7467ARQ-reel7 C40c to +120c 16-lead qsop rq-16
adt7467 rev. 0| page 79 of 80 notes
adt7467 rev. 0 | page 80 of 80 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04498C0C4/04(0)

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